參數(shù)資料
型號: CAT34RC02YITE13REV-E
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS
文件頁數(shù): 5/16頁
文件大?。?/td> 445K
代理商: CAT34RC02YITE13REV-E
CAT34RC02
5
Doc No. 1052, Rev. K
I
2
C BUS PROTOCOL
The I
2
C bus consists of two
wires
, SCL and SDA. The
two
wires
are connected to the supply (V
CC
) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to
transmit
a
0
and
releases it to
transmit
a
1
.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
START Condition
The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a
wake-up
call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Device Addressing
The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the
preamble
) are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A
2
, A
1
and A
0
, select one of eight possible
Slave devices. The last bit, R/
W
, specifies whether a
Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then
releases
the SDA
line durng the 9
th
clock cycle. If the Master acknowledges
in the 9
th
clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1
DEVICE ADDRESS
0
1
0
A2
A1
A0
R/W
0
1
1
0
A2
A1
A0
R/W
Normal Read and Write
Programming the Write
Protect Register
相關PDF資料
PDF描述
CAT34RC02PITE13REV-E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34RC02JITE13REV-E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34RC02PETE13REV-E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34RC02LETE13REV-E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34RC02LITE13REV-E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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