參數(shù)資料
型號(hào): CAT28C16ANI-20
英文描述: 16K-Bit CMOS PARALLEL E2PROM
中文描述: 16K的位CMOS并行E2PROM的
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 54K
代理商: CAT28C16ANI-20
1
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT28C16A
16K-Bit CMOS PARALLEL E
2
PROM
FEATURES
I
Fast Read Access Times: 200 ns
I
Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 100
μ
A Max.
I
Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
I
Fast Write Cycle Time: 10ms Max
I
End of Write Detection:
I
Hardware Write Protection
I
CMOS and TTL Compatible I/O
I
10,000 Program/Erase Cycles
I
10 Year Data Retention
I
Commercial, Industrial and Automotive
Temperature Ranges
DATA
Polling
5089 FHD F02
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS
Parallel E
2
PROM organized as 2K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling signals the start and end of the self-timed
write cycle. Additionally, the CAT28C16A features hard-
ware write protection.
The CAT28C16A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 24-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A4–A10
CE
OE
WE
A0–A3
I/O0–I/O7
I/O BUFFERS
2,048 x 8
E
2
PROM
ARRAY
VCC
DATA POLLING
Doc. No. 25033-00 2/98
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