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  • 參數(shù)資料
    型號(hào): CAT25C256Y14-1.8-GT2
    英文描述: 128K/256K-Bit SPI Serial CMOS EEPROM
    中文描述: 128K/256K-Bit SPI串行EEPROM中的CMOS
    文件頁(yè)數(shù): 6/12頁(yè)
    文件大?。?/td> 454K
    代理商: CAT25C256Y14-1.8-GT2
    CAT25C128/256
    6
    Document No. 1018, Rev. I
    Protected
    Blocks
    Unprotected
    Blocks
    Status
    Register
    WPEN
    WP
    WEL
    0
    X
    0
    Protected
    Protected
    Protected
    0
    X
    1
    Protected
    Writable
    Writable
    1
    Low
    0
    Protected
    Protected
    Protected
    1
    Low
    1
    Protected
    Writable
    Protected
    X
    High
    0
    Protected
    Protected
    Protected
    X
    High
    1
    Protected
    Writable
    Writable
    WRITE PROTECT ENABLE OPERATION
    WP
    : Write Protect
    WP
    is the Write Protect pin. The Write Protect pin will
    allow normal read/write operations when held high.
    When
    WP
    is tied low and the WPEN bit in the status
    register is set to “1”, all write operations to the status
    register are inhibited.
    WP
    going low while
    CS
    is still low
    will interrupt a write to the status register. If the internal
    write cycle has already been initiated,
    WP
    going low will
    have no effect on any write operation to the status
    register. The
    WP
    pin function is blocked when the WPEN
    bit is set to 0.
    HOLD
    : Hold
    The
    HOLD
    pin is used to pause transmission to the
    CAT25C128/256 while in the middle of a serial sequence
    without having to re-transmit entire sequence at a later
    time. To pause,
    HOLD
    must be brought low while SCK is
    low. The SO pin is in a high impedance state during the
    time the part is paused, and transitions on the SI pins will
    be ignored. To resume communication,
    HOLD
    is brought
    high, while SCK is low.
    (HOLD
    should be held high any
    time this function is not being used.)
    HOLD
    may be tied
    high directly to V
    cc
    or tied to V
    cc
    through a resistor. Figure
    9 illustrates hold timing sequence.
    STATUS REGISTER
    The Status Register indicates the status of the device.
    The
    RDY
    (Ready) bit indicates whether the CAT25C128/
    256 is busy with a write operation. When set to 1 a write
    cycle is in progress and when set to 0 the device
    indicates it is ready. This bit is read only.
    The WEL (Write Enable) bit indicates the status of the
    write enable latch . When set to 1, the device is in a Write
    Enable state and when set to 0 the device is in a Write
    Disable state. The WEL bit can only be set by the WREN
    instruction and can be reset by the WRDI instruction.
    The BP0 and BP1 (Block Protect) bits indicate which
    blocks are currently protected. These bits are set by the
    user issuing the WRSR instruction. The user is allowed
    to protect quarter of the memory, half of the memory or
    the entire memory by setting these bits. Once protected
    the user may only read from the protected portion of the
    array. These bits are non-volatile.
    Status Register Bits
    BP1
    Array Address
    Protected
    Protection
    BP0
    0
    0
    None
    No Protection
    0
    1
    25C128: 3000-3FFF
    25C256: 6000-7FFF
    Quarter Array Protection
    1
    0
    25C128: 2000-3FFF
    25C256: 4000-7FFF
    Half Array Protection
    1
    1
    25C128: 0000-3FFF
    25C256: 0000-7FFF
    Full Array Protection
    BLOCK PROTECTION BITS
    7
    6
    5
    4
    3
    2
    1
    0
    WPEN
    X
    X
    X
    BP1
    BP0
    WEL
    RDY
    STATUS REGISTER
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