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參數(shù)資料
| 型號(hào)： | CAT25C09LA-TE13 |
| 英文描述： | RF/Coaxial Connector; RF Coax Type:BNC; Contact Termination:Solder; Impedance:50ohm; Body Style:Straight Bulkhead Jack; RG Cable Type:58, 59, 179, 316 RoHS Compliant: Yes |
| 中文描述： | 1K/2K/4K/8K/16K SPI串行EEPROM中的CMOS |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 79K |
| 代理商： | CAT25C09LA-TE13 |
5
CAT25C11/03/05/09/17
Doc. No. 1017, Rev. J
SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
25C11/03/05/09/17. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
CS
:
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C11/
03/05/09/17 and
CS
high disables the CAT25C11/03/05/
09/17.
CS
high takes the SO output pin to high impedance
7
6
5
4
3
2
1
0
WPEN
1
1
BP2
BP1
BP0
WEL
RDY
STATUS REGISTER
BP2
BP1
BP0
0
0
0
Non-Protection
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
MEMORY PROTECTION
25C11
25C03
25C05
25C09
25C17
Q1
00-1F
00-3F
000-07F
000-0FF
000-1FF
Q2
Q3
Q4
H1
P0
Pn
20-3F
40-5F
60-7F
00-3F
00-0F
70-7F
40-7F
80-BF
C0-FF
00-7F
00-0F
F0-FF
080-0FF
100-17F
180-1FF
000-0FF
000-00F
1F0-1FF
100-1FF
200-2FF
300-3FF
000-1FF
000-01F
3E0-3FF
200-3FF
400-5FF
600-7FF
000-3FF
000-01F
7E0-7FF
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
WRITE PROTECT ENABLE OPERATION
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
05/09/17 draws ZERO current in the Standby mode. A
high to low transition on
CS
is required prior to any
sequence being initiated. A low to high transition on
CS
after a valid write sequence is what initiates an internal
write cycle.
WP
:
Write Protect
WP
is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When
WP
is
tied low and the WPEN bit in the status register is set to "1",
all write operations to the status register are inhibited.
WP
going low while
CS
is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated,
WP
going low will have no effect on any write
BYTE ADDRESS
Device
CAT25C11
CAT25C03
CAT25C05
CAT25C09
CAT25C17
Address Significant Bits
A6 - A0
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
A10 - A0
Address Don't Care Bits
A7
—
—
A15 - A10
A15 - A11
# Address Clock Pulse
8
8
8
16
16
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