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參數(shù)資料
| 型號(hào)： | CAT25C03LA-TE13 |
| 元件分類： | DRAM |
| 英文描述： | 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM |
| 中文描述： | 1K/2K/4K/8K/16K SPI 串行 互補(bǔ)型金屬氧化物 電可擦可編程只讀存儲(chǔ)器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 79K |
| 代理商： | CAT25C03LA-TE13 |
6
CAT25C11/03/05/09/17
Doc. No. 1017, Rev. J
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
operation to the status register. The
WP
pin function is
blocked when the WPEN bit is set to 0. Figure 10 illustrates
the
WP
timing sequence during a write operation.
HOLD
:
Hold
HOLD
is the HOLD pin. The
HOLD
pin is used to pause
transmission to the CAT25C11/03/05/09/17 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause,
HOLD
must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,
HOLD
is brought high, while SCK is low.
HOLD
should be held high any time this function is not
being used.
HOLD
may be tied high directly to V
CC
or tied
to V
CC
through a resistor. Figure 9 illustrates hold timing
sequence.
STATUS REGISTER
The Status Register indicates the status of the device.
The
RDY
(Ready) bit indicates whether the CAT25C11/
SK
SI
CS
SO
0
0
0
0
0
1
1
0
HIGH IMPEDANCE
SK
SI
CS
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1)
–
–
–
–
Note: Dashed Line= mode (1, 1)
–
–
–
–
03/05/09/17 is busy with a write operation. When set to
1 a write cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only the WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WEL bit can only be set by the WREN instruction and can
be reset by the WRDI instruction.
The BP0, BP1 and BP2 bits indicate which part of the
memory array is currently protected. These bits are set
by the user issuing the WRSR instruction. The user is
allowed to protect from one page to as much as half the
entire array. Once the three protection bits are set the
associated memory can be read but not written until the
protection bits are reset. These bits are non volatile.
The WPEN (Write Protect Enable) is an enable b it for the
WP
pin. The
WP
pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when
WP
is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C03LI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C03P | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C03P-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (256x8) 2K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C03PA | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C03PI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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