參數(shù)資料
型號: CAT24C16YIT3
英文描述: 1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
中文描述: 1 - KB的,是以2 KB,4 - KB的,8 - kB和16 KB的的CMOS串行EEPROM
文件頁數(shù): 2/17頁
文件大小: 361K
代理商: CAT24C16YIT3
CAT24C01/02/04/08/16
2
Doc. No. 1115, Rev. C
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
Units
1,000,000
100
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CCR
Read Current
Read, f
SCL
= 400 kHz
1
mA
I
CCW
I
SB
Write Current
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
1
mA
Standby Current
1
μ
A
I
L
I/O Pin Leakage
Pin at GND or V
CC
1
μ
A
V
IL
Input Low Voltage
-0.5
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
V
CC
2.5 V, I
OL
= 3.0 mA
0.4
V
V
OL2
Output Low Voltage
V
CC
< 2.5 V, I
OL
= 1.0 mA
0.2
V
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Max
Units
C
IN(3)
SDA I/O Pin Capacitance
V
IN
= 0 V
8
pF
C
IN(3)
I
WP(5)
Input Capacitance (other pins)
V
IN
= 0 V
6
pF
WP Input Current
V
IN
< V
IH,
V
CC
= 5.5 V
200
μ
A
V
IN
< V
IH,
V
CC
= 3.3 V
150
V
IN
< V
IH,
V
CC
= 1.8 V
100
V
IN
> V
IH
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
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