參數(shù)資料
型號(hào)： CAT24C164LIT3
英文描述： 16-Kb CMOS Serial EEPROM, Cascadable
中文描述： 16 KB的的CMOS串行EEPROM，可級(jí)聯(lián)
文件頁(yè)數(shù)： 4/16頁(yè)
文件大?。?/td> 556K
代理商： CAT24C164LIT3
CAT24C164
4
Doc. No. 1118, Rev. A
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-ON RESET (POR)
CAT24C164 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24C164 device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
The CAT24C164 can be made compatible with the
CAT24C16 by tying A2, A1 and A0 to V
SS
or by leaving
A2, A1 and A0 float.
WP:
The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C164 supports the Inter-Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C164
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver.
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular Slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Figure 2). The next three significant bits (A2, A1, A0)
are the device address bits and define which device or
which part of the device the Master is accessing (The
A1 bit must be the compliment of the A1 input pin signal).
Up to eight CAT24C164 devices may be individually ad-
dressed by the system. The next three bits are used as
the three most significant bits of the data word address.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9
th
clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
相關(guān)PDF資料
PDF描述
CAT24C164VP2I-GT3 16-Kb CMOS Serial EEPROM, Cascadable
CAT24C164VP2IT3 16-Kb CMOS Serial EEPROM, Cascadable
CAT24C164WI-GT3 16-Kb CMOS Serial EEPROM, Cascadable
CAT24C164WIT3 16-Kb CMOS Serial EEPROM, Cascadable
CAT24C164YI-GT3 16-Kb CMOS Serial EEPROM, Cascadable
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CAT24C164VP2IGT3 功能描述:電可擦除可編程只讀存儲(chǔ)器 16K-Bit Serial Cascadable RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
CAT24C164WGI-26781 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述:
CAT24C164WI 制造商:CSI 功能描述:
CAT24C164WIG 制造商:ON Semiconductor 功能描述:EEPROM Serial-I2C 16K-bit 2K x 8 2.5V/3.3V/5V 8-Pin SOIC N 制造商:CSI 功能描述:
CAT24C164WI-G 功能描述:電可擦除可編程只讀存儲(chǔ)器 16K-Bit Serial Cascadable RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*