參數(shù)資料
型號(hào): CAT24C043
英文描述: 4K,Supervisory Circuits with IIC Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer(帶4K IIC串行CMOS EEPROM,精密復(fù)位控制器和看門狗定時(shí)器的監(jiān)控電路)
中文描述: 4K的,與國際進(jìn)口監(jiān)控電路的CMOS串行EEPROM的,精密復(fù)位控制器和看門狗定時(shí)器(帶4K的進(jìn)口證的CMOS串行EEPROM的,精密復(fù)位控制器和看門狗定時(shí)器的監(jiān)控電路)
文件頁數(shù): 9/12頁
文件大?。?/td> 85K
代理商: CAT24C043
CAT24C163/083/043/023
9
Advanced
Doc. No. 25080-00 3/98 M-1
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 9. Immediate Address Read Timing
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24CXXX initiates the internal write cycle. ACK poll-
ing can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24CXXX is still busy with the write
operation,
no
ACK
CAT24CXXX has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
will
be
returned.
If
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V
CC
, the entire memory array is
protected and becomes read only. The CAT24CXXX
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device's failure to send an acknowledge
after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24CXXX is initiated in
the same manner as the write operation with one excep-
tion, that R/
W
bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
24C1601Fig.8
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