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參數(shù)資料
| 型號： | CAT24C03ZI-GT3 |
| 英文描述： | 1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM |
| 中文描述： | 1 - KB的，是以2 KB，4 - KB的，8 - kB和16 KB的的CMOS串行EEPROM |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 361K |
| 代理商： | CAT24C03ZI-GT3 |
CAT24C01/02/04/08/16
3
Doc No. 1115, Rev. C
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C.
Symbol
F
SCL
Parameter
Clock Frequency
Standard
Min
Fast
Units
kHz
Max
100
Min
Max
400
t
HD:STA
START Condition Hold Time
4
0.6
μ
s
t
LOW
Low Period of SCL Clock
4.7
1.3
μ
s
t
HIGH
High Period of SCL Clock
4
0.6
μ
s
t
SU:STA
START Condition Setup Time
4.7
0.6
μ
s
t
HD:DAT
Data In Hold Time
0
0
μ
s
t
SU:DAT
Data In Setup Time
250
100
ns
t
R
t
F(2)
SDA and SCL Rise Time
1000
300
ns
SDA and SCL Fall Time
300
300
ns
t
SU:STO
STOP Condition Setup Time
4
0.6
μ
s
t
BUF
Bus Free Time Between STOP and START
4.7
1.3
μ
s
t
AA
SCL Low to Data Out Valid
3.5
0.9
μ
s
t
DH
T
i(2)
Data Out Hold Time
100
100
ns
Noise Pulse Filtered at SCL and SDA Inputs
100
100
ns
t
SU:WP
WP Setup Time
0
0
μ
s
t
HD:WP
WP Hold Time
2.5
2.5
μ
s
t
WR
t
PU(2, 3)
Write Cycle Time
5
5
ms
Power-up to Ready Mode
1
1
ms
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
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