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參數(shù)資料
| 型號： | CAT1025YI-45TE13 |
| 英文描述： | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| 中文描述： | 監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM和手動復位 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 140K |
| 代理商： | CAT1025YI-45TE13 |
6
CAT1024, CAT1025
Doc. No. 3008, Rev. M
RESET CIRCUIT AC CHARACTERISTICS
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
7. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
AC TEST CONDITIONS
l
b
m
y
S
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e
m
a
a
P
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T
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m
i
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e
R
2
e
N
0
3
1
0
0
2
0
7
2
s
m
t
D
P
R
V
H
T
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a
D
t
p
O
T
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S
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R
o
3
e
N
5
s
μ
t
H
C
c
G
T
G
R
V
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C
a
h
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s
P
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R
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5
,
e
N
0
3
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h
M
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I
h
c
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R
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1
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N
0
0
1
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n
t
W
R
M
t
M
h
W
e
s
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R
M
1
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N
5
s
μ
D
R
y
a
D
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E
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o
p
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M
1
e
N
1
s
μ
G
N
I
M
I
T
P
U
-
R
E
W
O
P
6
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-
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0
7
2
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U
-
w
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P
0
7
2
s
m
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e
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a
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P
s
n
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C
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T
s
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P
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p
n
V
2
C
1
C
V
8
o
C
C
s
e
m
i
l
F
d
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s
R
t
p
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s
n
0
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e
g
a
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e
c
n
e
R
t
p
n
V
3
C
C
V
7
,
C
C
s
e
g
a
V
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c
n
e
R
t
p
O
V
5
C
C
d
a
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L
t
p
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I
p
:
0
1
c
o
C
L
=
S
t
e
C
L
O
F
;
A
m
3
=
0
RELIABILITY CHARACTERISTICS
Symbol
N
END(5)
Parameter
Reference Test Method
Min
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR(5)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP(5)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH(5)(7)
Latch-Up
JEDEC Standard 17
100
mA
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