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    參數(shù)資料
    型號(hào)： CAT1024YI-28-GT3
    英文描述： Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    中文描述： 監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM和手動(dòng)復(fù)位
    文件頁(yè)數(shù)： 10/20頁(yè)
    文件大小： 267K
    代理商： CAT1024YI-28-GT3
    CAT1024, CAT1025
    Doc. No. 3008 Rev. N
    10
    2007 Catalyst Semiconductor, Inc.
    Characteristics subject to change without notice
    ACKNOWLEDGE
    After a successful data transfer, each receiving
    device is required to generate an acknowledge. The
    acknowledging device pulls down the SDA line
    during the ninth clock cycle, signaling that it received
    the 8 bits of data.
    The CAT1024/25 responds with an acknowledge
    after receiving a START condition and its slave
    address. If the device has been selected along with
    a write operation, it responds with an acknowledge
    after receiving each 8-bit byte.
    When the CAT1024/25 begins a READ mode it
    transmits 8 bits of data, releases the SDA line and
    monitors the line for an acknowledge. Once it
    receives this acknowledge, the CAT1024/25 will
    continue to transmit data. If no acknowledge is sent
    by the Master, the device terminates data transmis–
    sion and waits for a STOP condition.
    WRITE OPERATIONS
    Byte Write
    In the Byte Write mode, the Master device sends the
    START condition and the slave address information
    (with the R/ˉˉ bit set to zero) to the Slave device. After
    the Slave generates an acknowledge, the Master sends
    a 8-bit address that is to be written into the address
    pointers of the device. After receiving another acknow-
    ledge from the Slave, the Master device transmits the
    data to be written into the addressed memory location.
    The CAT1024/25 acknowledges once more and the
    Master generates the STOP condition. At this time, the
    device begins an internal programming cycle to non-
    volatile memory. While the cycle is in progress,
    the device will not respond to any request from the
    Master device.
    Figure 5. Start/Stop Timing
    Figure 6. Acknowledge Timing
    Figure 7: Slave Address Bits
    START BIT
    SDA
    STOP BIT
    SCL
    ACKNOWLEDGE
    1
    START
    SCL FROM
    MASTER
    8
    9
    DATA OUTPUT
    FROM TRANSMITTER
    DATA OUTPUT
    FROM RECEIVER
    1
    0
    1
    0
    0
    0
    0
    R/W
    Default Configuration
    相關(guān)PDF資料
    PDF描述
    CAT1024YI-28T2 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-28T3 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-30 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-30-GT2 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-30-GT3 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    CAT1024YI-28T2 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-28T3 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
    CAT1024YI-28-T3 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 2K EEPROM - Tape and Reel
    CAT1024YI-28TE13 功能描述:監(jiān)控電路 2K bit 2.8V Ind Temp RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
    CAT1024YI30 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 2K EEPROM - Rail/Tube
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