參數(shù)資料
型號: CAT1023WI-25-GT2
元件分類: EEPROM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 6/21頁
文件大?。?/td> 278K
代理商: CAT1023WI-25-GT2
CAT1021, CAT1022, CAT1023
Doc. No. 3009 Rev. L
6
2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
RESET CIRCUIT AC CHARACTERISTICS
Symbol
t
PURST
t
RDP
t
GLITCH
MR Glitch
t
MRW
t
MRD
t
WD
Parameter
Power-Up Reset Timeout
V
TH
to RESET output Delay
V
CC
Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
MR Input to RESET Output Delay
Watchdog Timeout
Test Conditions
Note 2
Note 3
Note 4, 5
Note 1
Note 1
Note 1
Note 1
Min
130
5
1.0
Typ
200
1.6
Max
270
5
30
100
1
2.1
Units
ms
μs
ns
ns
μs
μs
sec
POWER-UP TIMING
(5), (6)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Test Conditions
Min
Typ
Max
270
270
Units
ms
ms
AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
Output Load
Test Conditions
0.2V
CC
to 0.8V
CC
10ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current Source: I
OL
= 3mA; C
L
= 100pF
RELIABILITY CHARACTERISTICS
Symbol
Parameter
N
END
Endurance
T
DR
Data Retention
V
ZAP
ESD Susceptibility
I
LTH
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
Max
Units
Cycles/Byte
Years
Volts
mA
(5)
(5)
(5)
(5)(7)
1,000,000
100
2000
100
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
相關(guān)PDF資料
PDF描述
CAT1023WI-25-GT3 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023WI-25T2 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023WI-25T3 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023WI-28-GT2 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023WI-28-GT3 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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