參數(shù)資料
型號(hào)： CAT1021ZD4E-25TE13
英文描述： CAP CER 33000PF 10% 50V X7R 1206
中文描述： 監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM中，手動(dòng)復(fù)位和看門(mén)狗定時(shí)器
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 149K
代理商： CAT1021ZD4E-25TE13
13
CAT1021, CAT1022, CAT1023
Doc No. 3009, Rev. K
Immediate/Current Address Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N + 1. For N = E = 255, the
counter will wrap around to zero and continue to clock
out valid data. After the CAT1021/22/23 receives its
slave address information (with the R/
W
bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1021/22/23 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/
W
bit set to one.
The CAT1021/22/23 then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a
STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1021/22/23 will continue to output an 8-bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT1021/22/23
address bits so that the entire memory array can be read
during one operation.
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 12. Sequential Read Timing
相關(guān)PDF資料
PDF描述
CAT1022ZD4E-25TE13 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023ZD4E-25TE13 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1021ZD4E-28TE13 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1022ZD4E-28TE13 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT1023ZD4E-28TE13 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CAT1021ZD4E-28TE13 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1021ZD4E-30TE13 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1021ZD4E-42TE13 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1021ZD4E-45TE13 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
CAT1021ZD4I-25 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
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