參數(shù)資料
型號： CAMELIA
英文描述： Camelia C1 LV 8M/CL 8M Preliminary [Updated 04/03. 36 Pages] Area Array Color CCD. 3500 x 2300. 12-bit. 2.7 F/s
中文描述： 卡梅利婭C1呂8M/CL分初步[更新04/03。 36頁]面陣彩色CCD。 3500 x 2300。 12位。 2.7幀/秒
文件頁數(shù)： 19/36頁
文件大小： 1699K
代理商： CAMELIA
19
CAMELIA C1 8M LVDS and CameraLink Cameras
5320A–IMAGE–04/03
Operation with Integration
Time Control: T=2
Integration is fully controlled by the user by the external signal ITC:
The falling edge of ITC activates the start of frame integration. This falling edge is
synchronized by the camera with a latency of Td (time delay equivalent to a readout
time for a line: see notes in Table 8 on page 17).
The rising edge of ITC activates the stop of frame integration. This rising edge is
synchronized by the camera with the same latency as Td.
Note: The ITC signal period must be greater than the sum of the integration time
(defined by ITC low) and frame readout time.
Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1
for Binning 4 x 4).
Figure 10.
LVDS Integration Time Control Timing Diagram
Line Timing
Duty cycle of the PCK is 50%
Rising and falling edges: 1.5 ns
Pixel clock PCK and Data rate are: 25 MHz in binning mode 1 x 1, 12.5 MHz in
binning mode 2 x 2 and 6.25 MHz in binning mode 4 x 4
Minimum setup time of Data, LEN and FEN, to the rising edge of PCK: 10 ns
Minimum hold time of Data, LEN and FEN, after the rising edge of PCK: 10 ns
Figure 11.
LVDS Line Timing Diagram
LEN
ITC
Frame
integration
Time set by RS-232
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Video lines
L
L
L
L
Video lines
M Pixels
Td
Td
Shutter
delay
Waiting
Frame readout
FEN
SHUTTER
LEN
PCK
...
...
...
...
DATA
1st Valid Pixel
Last Valid Pixel
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