參數(shù)資料
型號： CAME-PXB4360
英文描述： 10A SCRS
中文描述： 內(nèi)容可尋址存儲器單元
文件頁數(shù)： 45/66頁
文件大?。?/td> 869K
代理商： CAME-PXB4360
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Data Sheet
6-45
07.2000
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All communication with ALP is done using the data interface. The data interface consists of the
following signals, as shown in
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:
1)
DAT(15:1) are needed with ALP V1.1. DAT(32:17) are reserved for future use.
CAME will be accessed only if CE is low at the rising edge of CLK. If WE is low at the time, a
write cycle will be executed; if WE is high, a read cycle will be executed. The OE signal controls
the CAME output buffers for read accesses only. The EN16 signal determines data bus width,
which is 16-bit for EN16 at low level, and 32-bit otherwise. This signal is intended for static
adjustment of bus width.
Parity generation in 16-bit Mode extends over DAT(16..0) and ADR(3..0). In 32-bit Mode, it
extends over DAT(32..0) and ADR(3..0). In 32-bit interface mode, ADR(3) is not needed and
must be connected to ground; thus, parity generated over DAT(32..0) and ADR(2..0) is accepted
correctly. In both cases, DAT(0) is used as a parity line and completes the corresponding DAT
and ADR lines to odd parity. In 16-bit Mode, only the lower part of the data bus is used. The
upper bus half (index 17..32) is ignored during write accesses to CAME and is 0 during read
accesses.
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DAT(0)
Odd parity. Selected to create parity over ADR and DAT bidirectional
DAT(31..1)
1)
Data Bus
bidirectional
DAT(32)
Data Bus
bidirectional
ADR(2..0)
Address Bus
input
ADR(3)
Address Bus
input
WE
Write Enable
input
OE
Output Enable
input
CE
Chip Enable
input
CLK
Clock
input
EN16
Selection of bus width
input
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