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參數(shù)資料
| 型號： | CA3524E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Regulating Pulse Width Modulator |
| 中文描述： | 0.1 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDIP16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 206K |
| 代理商： | CA3524E |
8
CA1524, CA2524, CA3524
of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAl524’s, one must be designated as master, with R
T
C
T
set for the correct period. Each of the remaining units
(slaves) must have a C
T
of 1/2 the value used in the master
and approximately a 1010 longer R
T
C
T
period than the mas-
ter. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.
FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION
OF R
T
AND C
T
Error AmplIfIer Section
The error amplifier consists of a differential pair (Q56,Q57)
with an active load (Q61 and Q62) forming a differential
transconductance amplifier. Since Q61 is driven by a
constant current source, Q62, the output impedance R
OUT
,
terminal 9, is very high (
5M
).
The gain is:
A
V
= g
m
R = 8 l
C
R/2KT = 10
4
,
R
OUT
R
L
Since R
OUT
is extremely high, the gain can be easily
reduced from a nominal 10
4
(80dB) by the addition of an
external shunt resistor from terminal 9 to ground as shown in
Figure 6.
80
R
L
=
∞
FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE
CHARACTERISTICS.
where R =
, R
L
=
∞
, A
V
∝
10
4
R
OUT
+
R
L
T
T
)
10
5
10
4
10
3
1
10
10
2
10
3
10
4
OSCILLATOR PERIOD, t (
μ
s)
T
A
= +25
o
C
V+ = 8V - 40V
C
T
= 0.01
μ
F
C
T
= 0.002
μ
F
C
T
= 0.005
μ
F
C
T
= 0.001
μ
F
C
T
= 0.02
μ
F
C
T
= 0.05
μ
F
C
T
= 0.1
μ
F
V
70
60
50
40
0
o
90
o
P
R
L
= 3M
R
L
= 1M
R
L
= 300k
R
L
=100k
OPEN LOOP PHASE
OPEN LOOP GAIN
10
10
2
10
3
10
4
10
5
50
FREQUENCY (Hz)
The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated
amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.
Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good start-
ing point to determine the external poles is a 1000-pF
capacitor and a variable series 50-K
potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200
μ
A can pull this point to ground and shut off
both output drivers.
While feedback is normally applied around the entire regula-
tor, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regu-
lator applications if divided as shown in Figure 8. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF
COMPARATOR VOLTAGE (AT TERMINAL 9).
FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF AMBIENT TEMPERATURE.
O
48
40
32
24
16
8
0
COMPARATOR VOLTAGE (V)
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
T
A
= +25
o
C
V+ = 20V
C
T
= 2700pF
R
T
= 6.19k
f
OSC
= 60kHz
C
T
=1000pF
R
T
= 5k
f
OSC
= 20kHz
1.1
1.0
0.9
0.8
0.7
-75 -50 -25
0
25
50
75 100 125 150 175
O
AMBIENT TEMPERATURE (
o
C)
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