參數(shù)資料
型號： CA3338MZ
廠商： INTERSIL CORP
元件分類： DAC
英文描述： CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters
中文描述： PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDSO16
封裝： LEAD FREE, PLASTIC, MS-013-AA, SOIC-16
文件頁數(shù)： 3/10頁
文件大小： 240K
代理商： CA3338MZ
3
CA3338, CA3338A
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . .-0.5V to +8V
(V
DD
- V
SS
or V
DD
- V
EE
, Whichever is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7). . . . V
SS
- 0.5V to V
DD
+ 0.5V
Analog Pins (V
REF
+, V
REF
-, V
OUT
) . . . .V
DD
- 8V to V
DD
+ 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . .
±
20mA
Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V
Operating Conditions
Temperature Range (T
A
)
Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
90
100
θ
JC
(
o
C/W)
N/A
N/A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE Clocked at 20MHz, R
L
≥
1 M
,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
-
-
Bits
Integral Linearity Error
See Figure 4
CA3338
-
-
±
1
LSB
CA3338A
-
-
±
0.75
LSB
Differential Linearity Error
See Figure 4
CA3338
-
-
±
0.75
LSB
CA3338A
-
-
±
0.5
LSB
Gain Error
Input Code = FF
HEX
, See Figure 3
CA3338
-
-
±
0.75
LSB
CA3338A
-
-
±
0.5
LSB
Offset Error
Input Code = 00
HEX
; See Figure 3
-
-
±
0.25
LSB
DIGITAL INPUT TIMING
Update Rate
To Maintain
1
/
2
LSB Settling
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
For Low Glitch
DC
50
-
MHz
Update Rate
DC
20
-
MHz
Set Up Time t
SU1
Set Up Time t
SU2
Hold Time t
H
Latch Pulse Width t
W
Latch Pulse Width t
W
OUTPUT PARAMETERS
-
-2
-
ns
For Data Store
-
8
-
ns
For Data Store
-
5
-
ns
For Data Store
-
5
-
ns
V
REF
- = V
EE
= -2.5V, V
REF
+ = +2.5V
R
L
Adjusted for 1V
P-P
Output
From LE Edge
-
25
-
ns
Output Delay t
D1
Output Delay t
D2
Rise Time t
r
Settling Time t
S
Output Impedance
-
25
-
ns
From Data Changing
-
22
-
ns
10% to 90% of Output
10% to Settling to
1
/
2
LSB
V
REF
+ = 6V, V
DD
= 6V
-
4
-
ns
-
20
-
ns
120
160
200
Glitch Area
-
150
-
pV/s
Glitch Area
V
REF
- = V
EE
= -2.5V,V
REF
+ = +2.5V
-
250
-
pV/s
相關(guān)PDF資料
PDF描述
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