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參數(shù)資料
| 型號(hào)： | CA3338EZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 封裝： | LEAD FREE, PLASTIC, MS-001-BB, DIP-16 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CA3338EZ |
5
CA3338, CA3338A
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
0
) through D7 (weighted 2
7
),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
DD
and V
SS
, are shifted to operate between V
DD
and V
EE
. V
EE
optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
DD
and V
EE
supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
D2
gives the delay from the input changing to the output
changing (10%), while t
SU2
and t
H
give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given t
SU1
set up time to the LE falling edge,
and the t
H
hold time from the LE rising edge. The delay to
the output changing, t
D1
, is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
W
pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
REF
- this is the (-) full-
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
REF
+, the (+) full-scale reference.
In unipolar operation, V
REF
- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from V
REF
+ to V
REF
- (see V
REF
+ input current in
specifications), so V
REF
- should have a low impedance path
to ground.
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
Most Significant Bit
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
V
SS
Digital Ground
9
D
0
V
EE
Least Significant Bit. Input Data Bit
10
Analog Ground
11
V
REF
-
Reference Voltage Negative Input
12
V
OUT
Analog Output
13
V
REF
+
Reference Voltage Positive Input
14
COMP
Data Complement Control input. Active High
15
LE
Latch Enable Input. Active Low
16
V
DD
Digital Power Supply, +5V
INPUT DATA
LATCH
ENABLE
t
SU1
t
SU2
t
W
t
H
LATCHED
LATCHED
DATA
FEEDTHROUGH
FIGURE 1. DATA TO LATCH ENABLE TIMING
t
D1
t
D2
t
r
t
S
1
/
2
LSB
1
/
2
LSB
90%
10%
INPUT
DATA
LATCH
ENABLE
OUTPUT
VOLTAGE
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
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