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參數(shù)資料
| 型號(hào)： | CA3338E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 59K |
| 代理商： | CA3338E |
10-16
Dynamic Characteristics
Keeping the full-scale range (V
REF
+ - V
REF
-) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
delays. The V
REF
+ (and V
REF
- if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7F
HEX
to 80
HEX
for an 8 bit device), and can be
measured by displaying the output as the input code alter-
nates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each
1
/
8
scale transition (1F
HEX
to 20
HEX
, 3F
HEX
to 40
HEX
, etc.)
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160
in parallel with the load resis-
tance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
0
00
O
C
B
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
INTEGRAL LINEARITY
ERROR (SHOWN -)
STRAIGHT LINE
INPUT CODE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
A = IDEAL STEP SIZE (1/255 OF FULL
SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
A
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
ERROR
CLOCK
8 DATA BITS
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
V
DD
COMP
V
SS
CA3338
V
OUT
V
REF
+
V
EE
12
13
11
10
+5V
+2.5V
-2.5V
R1
R2
PROBE TIP
OR BNC
CONNECTOR
REMOTE
V
OUT
R3
V
REF
-
DIGITAL
GROUND
ANALOG
GROUND
+
+
+
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
FUNCTION
CONNECTOR
Probe Tip
BNC
BNC
BNC
R1
82
75
18
Short
R2
62
160
130
75
R3
N/C
93
75
50
V
OUT (P-P)
1V
1V
1V
0 79V
Oscilloscope Display
Match 93
Cable
Match 75
Cable
Match 50
Cable
NOTES:
2. V
OUT(P-P)
is approximate, and will vary as R
OUT
of D/A varies.
3. All drawn capacitors are 0.1
μ
F multilayer ceramic/4.7
μ
F tantalum.
4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
CA3338, CA3338A
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