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參數(shù)資料
| 型號： | CA3338AMZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MS-013-AA, SOIC-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CA3338AMZ |
6
CA3338, CA3338A
In bipolar operation, V
REF
- would be returned to a negative
voltage (the maximum voltage rating to V
DD
must be
observed). V
EE
, which supplies the gate potential for the
output drivers, must be returned to a point at least as
negative as V
REF
-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
REF
- with
an input code of 00
HEX
(zero scale output), and an output
equal to 255/256 of V
REF
+ (referred to V
REF
-) with an input
code of FFHEX (full scale output). The difference between the
ideal and actual values of these two parameters are the
OFFSET and GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
ideal step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1
LSB, the device is monotonic. (The output will always increase
for increasing code or decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs. See Figure 4.
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.
Dynamic Characteristics
Keeping the full-scale range (V
REF
+ - V
REF
-) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
delays. The V
REF
+ (and V
REF
- if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7F
HEX
to 80
HEX
for an 8 bit device), and can be
measured by displaying the output as the input code
alternates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each
1
/
8
scale transition (1F
HEX
to 20
HEX
, 3F
HEX
to 40
HEX
, etc.)
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160
in parallel with the load
resistance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
255/256
254/256
253/256
3/256
2/256
1/256
0
00
01
02
03
FD
FE
FF
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
OFFSET
ERROR
(SHOWN +)
O
R
+
R
-
GAIN ERROR
(SHOWN -)
INPUT CODE IN HEXADECIMAL (COMP = LOW)
FIGURE 3. D/A OFFSET AND GAIN ERROR
0
00
O
C
B
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
INTEGRAL LINEARITY
ERROR (SHOWN -)
STRAIGHT LINE
INPUT CODE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
A = IDEAL STEP SIZE (1/255 OF FULL
SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
A
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
ERROR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CA3338EZ | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| CA3338MZ | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| CA3338 | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters(CMOS視頻速度，8-Bit，50 MSPS，R2R D/A轉(zhuǎn)換器) |
| CA3338A | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters(CMOS視頻速度，8-Bit，50 MSPS，R2R D/A轉(zhuǎn)換器) |
| CA3420EZ | 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3338AMZ96 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16(W INDTEMP VID D/A 8BIT 50MHZ 0 75 LSB RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CA3338D | 制造商:Harris Corporation 功能描述: |
| CA3338E | 制造商:Rochester Electronics LLC 功能描述:16 PDIP INDTEMP VIDEO D/A 8BIT 50MHZ 1.0 LSB - Bulk 制造商:Intersil Corporation 功能描述:IC 8BIT DAC 3338 DIP16 制造商:Intersil Corporation 功能描述:CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| CA3338EZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16 INDTEMP VID D/A 8BIT 50MHZ 1 0 LSB RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CA3338M | 制造商:Intersil Corporation 功能描述:CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
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