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    參數(shù)資料
    型號: CA3310AM
    廠商: INTERSIL CORP
    元件分類: ADC
    英文描述: CMOS, 10-Bit, A/D Converters with Internal Track and Hold
    中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
    封裝: PLASTIC, MS-013AD, SOIC-24
    文件頁數(shù): 13/15頁
    文件大?。?/td> 120K
    代理商: CA3310AM
    6-18
    Other Accuracy Effects
    Linearity, offset, and gain errors are dependent on the
    magnitude of the full-scale input range, V
    REF
    + - V
    REF
    -.
    Figure 11 shows how these errors vary with full-scale range.
    The clocking speed is a second factor that affects conversion
    accuracy. Figure 12 shows the typical variation of linearity,
    offset, and gain errors versus clocking speed.
    Gain and offset drift due to temperature are kept very low by
    means of auto-balancing the comparator. The specifications
    show typical offset and gain dependency on temperature.
    There is also very little linearity change with temperature, only
    that caused by the slight slowing of CMOS with increasing
    temperature. At 85
    o
    C, for instance, the lLE and DLE would be
    typically those for a 20% faster clock than at 25
    o
    C.
    Power Supplies and Grounding
    V
    DD
    (+) and V
    SS
    (GND) are the digital supply pins: they
    operate all internal logic and the output drivers. Because the
    output drivers can cause fast current spikes in the V
    DD
    and
    V
    SS
    lines, V
    SS
    should have a low impedance path to digital
    ground and V
    DD
    should be well bypassed.
    Except for V
    DD
    +, which is a substrate connection to V
    DD
    , all
    pins have protection diodes connected to V
    DD
    and V
    SS
    :
    input transients above V
    DD
    or below V
    SS
    will get steered to
    the digital supplies. Current on these pins must be limited by
    external means to the values specified under maximum
    ratings.
    The V
    AA
    + and V
    AA
    - terminals supply the charge-balancing
    comparator only. Because the comparator is autobalanced
    between conversions, it has good low frequency supply
    rejection. It does not reject well at high frequencies, how-
    ever: V
    AA
    - should be returned to a clean analog ground, and
    V
    AA
    + should be RC decoupled from the digital supply.
    There is approximately 50
    of substrate impedance
    between V
    DD
    and V
    AA
    +. This can be used, for example, as
    part of a low-pass RC filter to attenuate switching supply
    noise. A 10pF capacitor from V
    AA
    + to ground would
    attenuate 30kHz noise by approximately 40dB. Note that
    back-to-back diodes should be placed from V
    DD
    to V
    AA
    + to
    handle supply to capacitor turn-on or turn-off current
    spikes.
    Figure 16 shows V
    AA
    + supply rejection versus frequency.
    Note that the frequency to be rejected scales with the clock:
    the 100Hz rejection with a 100kHz clock would be roughly
    equivalent to the 1kHz rejection with a 1MHz clock.
    The supply current for the CA3310 is dependent on clock
    frequency, supply voltage, and temperature. Figure 14
    shows the typical current versus frequency and voltage,
    while Figure 15 shows it versus temperature and voltage.
    Note that if stopped in auto-balance, the supply current is
    typically
    somewhat higher than if free-running. See
    Specifications.
    Application Circuits
    Differential Input A/D System
    As the CA3310 accepts a unipolar positive-analog input, the
    accommodation of other ranges requires additional circuitry.
    The input capacitance and the input energy also force using
    a low-impedance source for all but slow speed use. Figure
    20 shows the CA3310 with a reference, input amplifier, and
    input-scaling resistors for several input ranges.
    The ICL7663S regulator was chosen as the reference, as it
    can deliver less than 0.25V input-to-output (dropout) voltage
    and uses very little power. As high a reference as possible is
    generally desirable, resulting in the best linearity and
    rejection of noise at the CA3310.
    The tantalum capacitor sources the V
    REF
    current spikes
    during a conversion cycle. This relieves the response and
    peak current requirements of the reference.
    The CA3140 operational amplifier provides good slewing
    capability for high bandwidth input signals and can quickly
    settle the energy that the CA3310 outputs at its V
    lN
    terminal.
    It can also drive close to the negative supply rail.
    If system supply sequencing or an unknown input voltage is
    likely to cause the operational amplifier to drive above the
    V
    DD
    supply, a diode clamp can be added from pin 8 of the
    operational amplifier to the V
    DD
    supply. The minus drive
    current is low enough not to require protection.
    With a 2MHz clock (~150kHz sampling), Nyquist criteria would
    give a maximum input bandwidth of 75kHz. The resistor values
    chosen are low enough to not seriously degrade system band-
    width (an operational amplifier settling) at that clock frequency.
    If A/D clock frequency and bandwidth requirements are lower,
    the resistor values (and input impedance) can be made
    correspondingly higher.
    The A/D system would generally be calibrated by tying V
    lN
    - to
    ground and applying a voltage to V
    IN
    + that is 0.5 LSB (
    1
    /
    2048
    of full-scale range) above ground. The operational amplifier
    offset should be adjusted for an output code dithering between
    000
    16
    and 001
    16
    for unipolar use, or 100
    16
    and 101
    16
    for bipo-
    lar use. The gain would then be adjusted by applying a voltage
    that is 1.5 LSB below the positive full scale input, and adjusting
    the reference for an output dithering between 3FE
    16
    and
    3FF
    16
    .
    Note that R1 through R5 should be very well matched, as
    they affect the common-mode rejection of the A/D system.
    Also, if R2 and R3 are not matched, the offset adjust of the
    operational amplifier may not have enough adjustment range
    in bipolar systems.
    The common-mode input range of the system is set by the
    supply voltage available to the operational amplifier. The
    range that can be applied to the V
    IN
    - terminal can be
    calculated by:
    V
    IN
    - for the most negative,
    (V
    IN
    + -2.5V) - (
    )V
    REF
    + for the most positive.
    -------
    1
    +
    -------
    1
    +
    -------
    CA3310, CA3310A
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