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參數(shù)資料
| 型號(hào)： | CA3290E |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output |
| 中文描述： | DUAL COMPARATOR, 20000 uV OFFSET-MAX, 1200 ns RESPONSE TIME, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 347K |
| 代理商： | CA3290E |
5
Their gate source potentials (V
GS
) are supplied by a common
bus from the biasing circuit shown in the right hand portion of
the Schematic Diagram. The currents supplied by Q
10
and
Q
12
are twice those supplied by Q
9
and Q
11
. The transistor
geometries are appropriately scaled to provide the requisite
currents with common V
GS
applied to Q
9
through Q
12
.
Operating Considerations
Input Circuit
The use of MOS transistors in the input stage of the CA3290
series circuits provides the user with the following features
for comparator applications:
1. Ultra high input impedance (
1.7T
);
2. Theavailabilityofcommonmoderejectionforinputsignals
at potentials below that of the negative power supply rail;
3. Retentionoftheinphaserelationshipoftheinputandout-
put signals for input signals below the negative rail.
Although the CA3290 employs rugged bipolar (zener) diodes
for protection of the input circuit, the input terminal currents
should not exceed 1mA. Appropriate series connected
limiting resistors should be used in circuits where greater
current flows might exist, allowing the signal input voltage to
be greater than the supply voltage without damaging the
circuit.
Output Circuit
The output of the CA3290 is the open collector of an n-p-n
transistor, a feature providing flexibility in a broad range of
comparator applications. An output ORing function can be
implemented by parallel connection of the open collectors.
An output pull-up resistor can be connected to a power
supply having a voltage range within the rating of the
particular CA3290 in use; the magnitude of this voltage may
be set at a value which is independent of that applied to the
V+ terminal of the CA3290.
Parasitic Oscillations
The ideal comparator has, among other features, ultra high
input impedance, high gain, and wide bandwidth. These
desirable characteristics may, however, produce parasitic
oscillations unless certain precautions are observed to
minimize the stray capacitive coupling between the input and
output terminals. Parasitic oscillations manifest themselves
during the output voltage transition intervals as the
comparator switches states. For high source impedances,
stray capacitance can induce parasitic oscillations. The
addition of a small amount (1mV to 10mV) of positive
feedback (hysteresis) produces a faster transition, thereby
reducing the likelihood of parasitic oscillations. Furthermore,
if the input signal is a pulse waveform, with relatively rapid
rise and fall times, parasitic tendencies are reduced.
When dual comparators, like the CA3290, are packaged in an
8 lead configuration, the output terminal of each comparator is
adjacent to an input terminal. The lead-to-lead capacitance is
approximately 1pF, which may be sufficient to cause
undesirable feedback effects in certain applications. Circuit
factors such as impedance levels, supply voltage, switching
rate, etc., may increase the possibility of parasitic oscillations.
To minimize this potential oscillatory condition, it is
recommended that for source impedances greater than 1k
a
capacitor (
≥
1pF - 2pF) be connected between the appropriate
input terminal and the output terminal. (See Figure 1.)
If either comparator is unused, its input terminals should also
be tied to either the V+ or V- supply rail.
Typical Applications
Light Controlled One-Shot Timer
In Figure 5 one comparator (A
1
) of the CA3290 is used to
sense a change in photo diode current. The other
comparator (A
2
) is configured as a one-shot timer and is
triggered by the output of A
1
. The output of the circuit will
switch to a low state for approximately 60 seconds after the
light source to the photo diode has been interrupted. The
circuit operates at normal room lighting levels. The
sensitivity of the circuit may be adjusted by changing the
values of R
1
and R
2
. The ratio of R
1
to R
2
should be
constant to insure constant reverse voltage bias on the
photo diode.
V+
D
2
D
1
V
I
+
I
1
50
μ
A
Q
P1
Q
2
Q
5
I
2
100
μ
A
Q
3
Q
6
I
3
50
μ
A
I
4
100
μ
A
V
I
-
D
3
D
4
V
O
Q
8
V-
Q
P4
Q
7
FIGURE 4. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO
COMPARATORS
+
-
+15V
A
2
CA3290
7
6
5
+15V
3.3k
60M
1.0
μ
F
10k
140k
+
-
A
1
CA3290
1
+15V
1N914
8
4
0.01
μ
F
1N914
+15V
3
2
1M
+15V
15k
1.5M
2M
15
k
C30809
X 60s TIME
R
1
R
2
FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER
CA3290, CA3290A
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