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參數(shù)資料
| 型號(hào)： | CA3282AS1 |
| 廠(chǎng)商： | INTERSIL CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | Octal Low Side Power Driver with Serial Bus Control |
| 中文描述： | 1 A 8 CHANNEL, SIPO BASED PRPHL DRVR, PZFM15 |
| 封裝： | PLASTIC, MO-048, SIP-15 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | CA3282AS1 |
3
Output Three State Leakage
Current
I
OL
V
DD
= 5.25V, 0 < V
O
< V
DD
,
CE Pin Held High
-10
-
+10
μ
A
Output Capacitance
C
OUT
0 < V
O
< V
DD
, CE Pin Held High
-
-
20
pF
Electrical Specifications
V
DD
= 5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Serial Peripheral Interface Timing
(See Figure 1B)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Frequency
f
OPER
D.C.
Note 4
3.0
MHz
Enable Lead Time
(2)
t
LEAD
-
<100
200
ns
Enable Lag Time
(3)
t
LAG
-
<100
200
ns
Clock HIGH Time
(4)
t
wSCK
H
-
50
100
ns
Clock LOW Time
(5)
t
wSCK
L
-
50
100
ns
Data Setup Time
(6)
t
SU
-
20
50
ns
Data Hold Time
(7)
t
H
-
20
50
ns
Enable Time
(8)
t
EN
-
50
100
ns
Disable Time
(9)
t
DIS
-
150
300
ns
Data Valid Time
(10)
t
V
-
75
150
ns
Output Data Hold Time
(11)
t
HO
0
50
-
ns
Rise Time (MISO Output)
(12)
t
rSO
V
DD
= 20% to 70%, C
L
= 200pF
-
35
100
ns
Rise Time SPI Inputs (SCK, MOSI, CE)
(12)
t
rSI
V
DD
= 20% to 70%, C
L
= 200pF
-
-
50
ns
Fall Time (MISO Output)
(13)
t
fSO
V
DD
= 70% to 20%, C
L
= 200pF
-
45
100
ns
Fall Time SPI Inputs (SCK, MOSI, CE)
(13)
t
fSI
V
DD
= 70% to 20%, C
L
= 200pF
-
-
50
ns
NOTES:
3. Refer to Figure 4A for I
OUT
current vs V
SAT
voltage. Typical r
DS(ON)
values are given for -40
o
C, 25
o
C, 105
o
C and 125
o
C temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
CE
SCK
MSB 6 5 4 3 2 1 LSB
(CPOL = 0, CPHA = 1)
INTERNAL STROBE FOR DATA CAPTURE
CA3282
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