
7-41
Specifications CA3277
DATA COMPARATOR
Data Comp Thd
V
BATT
- 3.6
V
BATT
-2.9
V
BATT
-2.2
V
Data Comp Hysteresis
-
200
-
mV
DATA OUT Low
V
OL
V
OH
V
BATT
= 16V, V
DATA IN
= (V
BATT
-5V)
V
BATT
= 16V, V
DATA IN
= 16V
-
-
0.15
V
DATA OUT High
V
OUT1
-0.15
-
5.25
V
DATA OUT Low Sink Current
I
OL
I
OH
V
DATA IN
Low
V
DATA IN
High
-
1
-
mA
DATA OUT High Source Current
-
-50
-
μ
A
IGNITION COMPARATOR
Ign Comp Thd
5.5
6
6.5
V
Ign Comp Hysteresis
-
200
-
mV
IGN OUT Low
V
OL
V
OH
I
OL
I
OH
-
-
0.15
V
IGN OUT High
4.6
5.25
V
IGN OUT Low Sink Current
V
IGN IN
Low
V
IGN IN
High
-
1
-
mA
IGN OUT High Source Current
-
-70
-
μ
A
OTHER PARAMETERS
Idle Current
I
Q
V
BATT
= 12.6V, No Loads, V
EN
= V
IGN IN
= 0V
Ramp V
BATT
Up Until OUT1 and OUT2 Shut-
down
-
500
800
μ
A
Over-Voltage Shutdown
V
BATT(OVSD)
19
20.5
23
V
Thermal Shutdown
T
J
-
150
-
o
C
Ripple Rejection
1V
PP
at 3kHz on BATT INPUT, Measure AC
Ripple on OUT1, OUT2
45
55
-
dB
NOTES:
1. For negative voltages on the BATT and IGN IN inputs, current drain is primarily reverse junction leakage, except when DATA IN, CUR
OUT, ENABLE and RESET are directly connected to BATT. (Note 2)
2. For negative voltage DATA IN, CUR OUT, ENABLE and RESET interface to NPN or equivalent on-chip structures; providing a forward
junction for current conduction into the IC. Negative current must be limited by the impedance of the external connection. This is also the
case where these terminals are interconnected to BATT, Normal application does not require the BATT connection, except for DATA IN
where a series diode for reverse current blocking may be used. (see Description text information)
3. Refer to the Electrical Characteristic TABLE for all Self-Limiting values.
4. Dissipation, approximately equals: P
D
≈
[(V
IN
I
IN
) + (V
CUR OUT
I
CUR OUT
) - 5(I
OUT1
+I
OUT2
)], where I
IN
V
IN
is IGN IN and BATT input dissi-
pation and V
OUT1
~
V
OUT2
~
5V. This assumes neglibible dissipation for the Ignition Comp., Reset and Data Comp. Outputs.
5. Dropout Voltage is V
DO1
= (V
BATT
- V
OUT1
) for REG. OUT1 and V
DO2
= (V
BATT
- V
OUT2
) for REG. OUT2
6. Reset Delay Time, t
RST
is the time period that the RESET (Pin 8) is low following the discharge of the CRST capacitor to ground. For test
evaluation, the CRST pin may be discharged repetitively with a transistor switch. The RESET pin switches from low to high when the
CRST pin is charged to approximately 3V. Normal ATE testing measures the source charging current. which is typically 10
μ
A. For any
other value of Capacitor the charge time, t for reset is determined as follows: t
~
308C, where C is in
μ
F and t is in milliseconds.
(i.e. C = 0.47
μ
F, t = 141ms)
Electrical Specifications
T
A
= -40
o
C to +85
o
C, V
BATT
= 13.5V, ENABLE ON (V
EN
= 3.5V), IGN IN connected to BATT, OUT1 and
OUT2 bypassed with 20
μ
F to GND, DATA IN connected through 250
to BATT, LOADS: OUT1 = 50mA,
OUT2 = 80mA; Unless Otherwise Specified (Refer to Figure 4 Test Circuit)
(Continued)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS