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參數(shù)資料
| 型號： | CA3274E |
| 廠商： | INTERSIL CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | Current Limiting Power Switch with Current Limiter Sense Flag |
| 中文描述： | 0.2 A BUF OR INV BASED PRPHL DRVR, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 27K |
| 代理商： | CA3274E |
10-42
Specifications CA3274
Absolute Maximum Ratings
Thermal Information
Operating Drive Supply, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
Maximum Output Current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . .200mA
Control, Sense Input. . . . . . . . . . . . . . . . . . . Gnd - 0.5V, V
CC
+ 0.5V
Signal, Power Differential Ground Voltage
. . . . . . . . . . . . . . . . . . . ±
1V
Thermal Resistance
Plastic DIP Package 8 Lead . . . . . . . . . . . . . . . . . . . . . 130
o
C/W
Power Dissipation, P
D
Up to 70
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630mW
Above 70
o
C . . . . . . . . . . . . . . . . . . . .Derate linearly at 7.7mW/
o
C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
Storage Temperature Range. . . . . . . . . . . . . . . . . .-55
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16in. (1.59mm
±
0.79mm) from
case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
θ
JA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Current: S1 = 2
I
CCH
Control = High (Output On)
-
-
25
mA
I
CCL
Control = Low (Output Off)
-
-
5
mA
Control Input: S1 = 3
V
THDH
Thd. Voltage, High
-
-
3.5
V
V
THDL
Thd. Voltage, Low
0.9
-
-
V
V
THDH
-V
THDL
Hysteresis
0.4
0.65
2.0
V
I
IL
Leakage, 0.0 to 5.5V
-20
-
+20
μ
A
Driver In, Out (Pin 6, 5): S1 = 3
V
SAT
Output Saturation Voltage, I
CC1
= 200mA,
V
CONTROL
= High
-
-
0.5
V
I
LEAK
Collector Output Leakage, V
CONTROL
=
Low
-
-
100
μ
A
Flag Output Low: S1 = 2
V
FSAT
V
SENSE
= High, I
FLAG
= 3mA
-
-
0.8
V
Flag Output High: S1 = 3
V
FLEAK
Output Leakage, V
CC
= V
FLAG
= 10V
-
-
10
μ
A
Prop. Delay: S1 = 1
t
ON
, t
OFF
Control In to Drive Out
-
5
-
μ
s
t
FLAG
Drive Off to Flag Off
-
10
-
μ
s
t
D
Flag Delay from Control In
150
-
600
μ
s
Sense Input Thd. Level: S1 = 1
V
SENTHD
310
335
360
mV
Power Supply Rejection Ratio
PSSR
50
-
-
dB
NOTES:
1. Refer to Figure 3 Test Diagram for electrical test connections.
2. Refer to Figure 2 Timing Diagram for logic switching and prop delay.
3. Unless otherwise specified: V
CC
= V
CC1
= V
CC2
= 7V to 10V;
V
SENSE
= “Low”; V
CONTROL
= “Low”;
Control in levels are defined as “Low” equals 0.0V and “High” equals 5.0V.
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