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參數(shù)資料
| 型號(hào)： | CA3224E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Automatic Picture Tube Bias Control Circuit |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP22 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 62K |
| 代理商： | CA3224E |
8-58
Test Circuit
Device Description and Operation
(See Figures 1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse out-
put goes high. This is used to set the RGB drive of the com-
panion chroma/luma circuit to black level. The auto-bias pulse
stays high for 7 horizontal periods during the auto-bias cycle.
On the 15th horizontal sync pulse, the internal logic initiates
the setup interval. During the setup interval, the cathode cur-
rent is increased to a reference value (A in Figure 5) through
the action of the grid pulse. The cathode current causes a
voltage drop across R
S
. This voltage drop, together with the
program pulse output results in a reference voltage at V
S
(summing point) which causes capacitor C
1
to charge to a
voltage proportional to the reference cathode current. The
setup interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output goes
high, which through the grid pulse amplifier/inverter, causes
the cathode current to decrease. The decrease in cathode
current results in a positive recovered voltage pulse with
respect to the setup reference level at the V
S
summing point.
The positive recovered voltage pulse is summed with a nega-
tive voltage pulse caused by the program pulse output going
low (cutting off Diode D
1
and switching in resistors R
1
and
R
2
). Any difference between the positive and negative pulses
is fed through capacitor C
1
to the transconductance amplifier.
The difference signal is amplified in the transconductance
amplifier and charges the hold capacitor C
2
, which, through
the buffer amplifier, adjusts the bias on the driver circuit.
Components R
S
, R
1
, and R
2
must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
V
OUT2
3.65K
0.12
μ
F
A
S
1
B
1
22
21
20
19
18
17
16
15
14
13
12
3.65K
0.12
μ
F
A
S
1
B
V
OUT1
3.65K
0.12
μ
F
A
S
1
B
V
OUT3
47
μ
F
3.32K
+20V
1.50K
+10V
1.5K
A
S
2
B
2
3
4
5
6
7
8
9
10
11
V
IN1
V
IN2
V
IN3
VERTICAL
INPUT
HORIZONTAL
INPUT
CA3224E
0.047
μ
F
0.047
μ
F
0.047
μ
F
20K
1.0K
+
+10V
V
BIAS
CHAN
1 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
1 OUT
CHAN
2 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
2 OUT
CHAN
3 IN
FREQ
COMP
HOLD
CAPACITOR
CHAN
3 OUT
2
3
21
20
4
5
19
18
6
7
17
16
x 1
x 1
x 1
+
-
g
M
BUFFER
AMP
AMPLIFER
NO. 3
BUFFER
AMP
AMPLIFER
NO. 2
BUFFER
AMP
AMPLIFER
NO. 1
1
12
2
3
3
3
2
1
V
REF
MODE
SWITCH
LOGIC
BIAS
1
9
22
V
CC
15
8
10
11
12
13
14
GND
GND
V
REF
BYPASS
VERT
IN
HORIZ
IN
AUTO
BIAS
LEVEL
ADJUST
AUTO
BIAS
PULSE
OUT
PROG
PULSE
OUT
GRID
PULSE
OUT
MODE SWITCH
STATE
SET-UP
SENSE
OPEN
1
2
3
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
+
-
g
M
+
-
g
M
CA3224E
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3224E WAF | 制造商:Harris Corporation 功能描述: |
| CA3224E_02 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Automatic Picture Tube Bias Control Circuit |
| CA3225M01 | 制造商:Eaton Corporation 功能描述:CA3225 with mtg hardware,Ln/Ld terminals |
| CA3227 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz |
| CA3227_02 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz |
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