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參數(shù)資料
| 型號： | CA3194E |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Single Chip PAL Luminance/Chroma Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 98K |
| 代理商： | CA3194E |
7-58
Specifications CA3194
Saturation Control Range (Terminal 3)
For control characteristic, see Figure 10.
0 - 5
V
DC
Maximum Chroma Output Voltage (Terminal 2)
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust V
C
and V
S
for maximum Pin 2 output.
2.5
V
P-P
OSCILLATOR SECTION
Pull-In Range
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust C
X
for HI/LO f
OSC
without Chroma signal.
Apply signal to lock.
±
500
Hz
Static Phase Error
2
Deg./
100Hz
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
Chroma Input: Burst =100mV, Chroma = 220mV
P-P
,V
.
Adjust V
C
for V18 = 1V. Read V15. Calculate V18/V15.
10
Ratio
B-Y Demodulator Conversion Gain
Chroma Input: Burst = 100mV
P-P
, U
. Read V16 and V14.
Calculate V16/V14. V
C
remains as for R-Y gain.
18
Ratio
G-Y/B-Y Matrix Ratio
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, U
read V17 and V16, Calculate V17/V16. V
C
remains as above.
0.2
Ratio
G-Y/R-Y Matrix Ratio
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, V
.
Read V17 and V18. Calculate V17/V18. V
C
remains as above.
0.5
Ratio
Sub-Carrier and Harmonic Content at Outputs
No Chroma or Luma Input. Read residual carrier at outputs.
30
mV
P-P
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
2 - 5
V
Burst Gate Pulse
6.5 - V
CC
V
NOTES:
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
Electrical Specifications
T
A
= +25
o
C, V
CC
= 12V, V
S
= 2.85V, V
C
= 2.85V, V
AB
= V
PB
= V
CC
, V
B
adjusted for V
18
= 6.3V, C
X
adjusted
for F
OSC
= 4.43361875MHz, Sandcastle: V
BG
= 8.0V, V
BLANK
= 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit
(Continued)
PARAMETER
TEST CONDITIONS
TYPICAL
VALUE
UNITS
Circuit Description
(See Block Diagram and Figure 20)
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
cuits are controlled from pins 24 and 19.
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