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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CA3102M |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/11闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OP AMP DUAL HI FREQ 14-SOIC |
| 妯欐簴鍖呰锛� | 50 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 宸垎 |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 澧炵泭甯跺绌嶏細 | 1.35GHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 13.5µA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 250µV |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-SOIC |
| 鍖呰锛� | 绠′欢 |
2
611.7
October 12, 2005
Absolute Maximum Ratings
Thermal Information
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 2)
胃
JA (
oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
205
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in 鈥淎bsolute Maximum Ratings鈥� may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2.
胃JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25
oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage (Figures 1, 4)
VIO
-
0.25
5.0
mV
Input Offset Current (Figure 1)
IIO
I3 = I9 = 2mA
-
0.3
3.0
渭A
Input Bias Current (Figures 1, 5)
IB
-
13.5
33
渭A
Temperature Coefficient
Magnitude of Input Offset Voltage
-1.1
-
渭V/oC
DC CHARACTERISTICS FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 6)
VBE
VCE = 6V, IC = 1mA
674
774
874
mV
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
VCE = 6V, IC = 1mA
-
-0.9
-
mV/oC
Collector Cutoff Current (Figure 7)
ICBO
VCB = 10V, IE = 0
-
0.0013
100
nA
Collector-to-Emitter Breakdown Voltage
V(BR)CEO
IC = 1mA, IB = 0
15
24
-
V
Collector-to-Base Breakdown Voltage
V(BR)CBO
IC = 10渭A, IE = 0
20
60
-
V
Collector-to-Substrate Breakdown Voltage
V(BR)CIO
IC = 10渭A, IB = IE = 0
20
60
-
V
Emitter-to-Base Breakdown Voltage
V(BR)EBO
IE = 10渭A, IC = 0
5
7
-
V
DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
1/f Noise Figure (For Single Transistor)
(Figure 12)
NF
f = 100kHz, RS = 500惟,
IC = 1mA
-1.5
-
dB
Gain Bandwidth Product (For Single
Transistor) (Figure 11)
fT
VCE = 6V, IC = 5mA
-
1.35
-
GHz
Collector-Base Capacitance (Figure 8)
CCB
IC = 0,
VCB = 5V
Note 3
-
0.28
-
pF
Note 4
-
0.15
-
pF
Collector-Substrate
Capacitance (Figure 8)
CCI
IC = 0, VCI = 5V
-
1.65
-
pF
Common Mode Rejection Ratio
CMRR
I3 = I9 = 2mA
-
100
-
dB
AGC Range, One Stage (Figure 2)
AGC
Bias Voltage = -6V
-
75
-
dB
Voltage Gain, Single-Ended Output
(Figures 2, 9, 10)
A
Bias Voltage = -4.2V,
f = 10MHz
18
22
-
dB
螖V
IO
螖T
----------------
螖V
BE
螖T
---------------
CA3102
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