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參數(shù)資料
| 型號(hào)： | CA3096C |
| 廠商： | Intersil Corporation |
| 英文描述： | NPN/PNP Transistor Arrays |
| 中文描述： | npn型/ PNP晶體管陣列 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | CA3096C |
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12
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
Typical Performance Curves
(Continued)
C
BIAS VOLTAGE (V)
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
C
BE
C
BI
C
BC
0
Metallization Mask Layout
CA3096H
40
30
20
10
0
40
30
20
10
0
37-45
(0.940-1.143)
4-10 (0.102-0.254)
37-45
(0.940-1.143)
Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mils (10
-3
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
CA3096, CA3096A, CA3096C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CA3096CE | NPN/PNP Transistor Arrays |
| CA3096E | NPN/PNP Transistor Arrays |
| CA3096M | NPN/PNP Transistor Arrays |
| CA3097 | THYRISTOR/TRANSISTOR ARRAY |
| CA3098 | Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3096CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NPN/PNP Transistor Arrays |
| CA3096CM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CA3096CM96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CA3096E | 制造商:HARRIS 功能描述:3096 |
| CA3096E 91 | 制造商:HAR 功能描述:CA3096N |
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