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參數(shù)資料
| 型號： | C9835CYT |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 低電磁干擾時鐘發(fā)生器英特爾移動133兆赫/ 3的SO - DIMM芯片系統(tǒng) |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 343K |
| 代理商： | C9835CYT |
C9835
Document #: 38-07303 Rev. **
Page 13 of 18
Notes:
32. The time specified is measured from when all V
DD
’
s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the
specifications.
33. Measured from when both SEL1 and SEL0 are switched to low (disable).
34. Device designed for Typical Duty Cycle of 50%.
TLOW
Tr / Tf
TSKEW
TCCJ
DOT and USB
TPeriod
PCI(_F, 1:6) low time
[31]
PCI(_F, 1:6) rise and fall times
[27]
(Any PCI) to (Any PCI) Skew
[26,29]
PCI(_F, 1:6) Cycle to Cycle Jitter
[26,29]
12.0
0.5
12.0
0.5
12.0
0.5
ns
ns
ps
ps
2.0
500
500
2.0
500
500
2.0
500
500
DOT and USB (48M[0,1]) period
(conforms to +167 ppm max)
[25,26]
DOT and USB rise and fall times
[27]
DOT and USB Cycle to Cycle Jitter
[26,29]
VCH_CLK Cycle to Cycle Jitter
[26]
20.8299 20.8333 20.8299 20.8333
20.829
20.833
ns
Tr / Tf
TCCJ
TCCJ
REF
TPeriod
Tr / Tf
TCCJ
1.0
4.0
500
250
1.0
4.0
500
250
1.0
4.0
500
250
ns
ps
ps
REF period
[25,26]
REF rise and fall times
[27]
REF Cycle to Cycle Jitter
[26]
69.8413
1.0
71.0
4.0
1000
69.8413
1.0
71.0
4.0
1000
69.8413
1.0
71.0
4.0
1000
ns
ns
ps
tpZL, tpZH
tpLZ, tpHZ
tstable
Tduty
Output enable delay (all outputs)
[28]
Output disable delay (all outputs)
[33]
All clock stabilization from power-up
[32]
Duty cycle for all outputs
[34]
1.0
1.0
10.0
10.0
3
55
1.0
1.0
10.0
10.0
3
55
1.0
1.0
10.0
10.0
3
55
ns
ns
ms
%
45
45
45
AC Parameters
(continued)
Parameter
Description
133 MHz Host
Min.
100 MHz Host
Min.
66 MHz Host
Min.
Units
Max.
Max.
Max.
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