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參數(shù)資料
| 型號(hào)： | C9827HY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | High Performance Pentium 4 Clock Synthesizer |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 171K |
| 代理商： | C9827HY |
C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 10 of 25
Approved Product
Maximum Lumped Capacitive Output
Loads
Clock
Max Load
30
30
30
20
10
30
Table 5
Units
pF
pF
pF
pF
pF
pF
PCI Clocks
3V66 (0,1)
66B(0:2)
48MUSB Clock
48MDOT
REF Clock
Maximum Ratings1
Input Voltage Relative to VSS:
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
VSS-0.3V
-65
°
C to + 150
°
C
0
°
C to +85
°
C
3.5V
Note 1: The voltage on any input or I/o pin cannot exceed the
power pin during power-up. Power supply sequencing is NOT
required.
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK Measurement Point
R
ref
R
tA1
CLK
CLK#
Mult0
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
Lumped Test Load Configuration
Component
R
tA1
, R
tA2
R
LA1
, R
LA2
T
PCB
R
LB1
, R
LB2
R
D
R
tB1
, R
tB2
C
LA
, C
LB
R
ref
0.7 Volt Amplitude Value
33
49.9
3” 50
Z
∞
∞
0
2pF
475
w/mult0=1
1.0 Volt Amplitude Value
0
∞
3” 50
Z
63
470
33
2 pF
221
w/mult0=0
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| C9827JT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC |
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