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參數(shù)資料
| 型號： | C9812DYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 268K |
| 代理商： | C9812DYB |
Low EMI Clock Generator for Intel
810E Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 7 of 18
APPROVED PRODUCT
C9812
Serial Control Registers
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “
Command Code
“
byte, and
2) “
Byte Count
” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register
(1=Enable, 0=Disable, Default=07)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
1
1
1
Pin#
-
-
-
-
-
26
25
49
Description
Reserved
Reserved
Reserved
Reserved
Spread spectrum mode
DOT
USB
CPU2_ITP
Byte 2: PCI Clock Register
(1=Enable, 0=Disable, Default=FE)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Pin#
20
19
18
16
15
13
12
-
Description
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
Byte 1: SDRAM Clock Register
(1=Enable, 0=Disable, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
36
37
39
40
42
43
45
46
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Reserved Register
(Default=00)
Byte 4: Reserved Register
(Default=00)
Byte 5: SSCG Control Register
(Default=00)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
Spread Mode (0=down, 1=center)
Ref. Table 4
Ref. Table 4
Reserved
Reserved
Reserved
Reserved
Reserved
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