
GATE SPECIFICATIONS
TAPPB0028EA
TAPPB0088EA
TAPPC0115EA
TAPPC0116EA
Figure 1: C9016-2x Series
Gate Time Input / Output Characteristics
Figure 2: C9016-2x Series
Time Sequence
Figure 3: C9546
·
C9547 Series
Gate Time Input / Output Characteristics
Figure 4: C9546
·
C9547 Series
Time Sequence
Parameter
Normal Mode
Gate Mode
Level
Input Impedance
Pulse Width
A
Repetition Rate
B
(Max)
when MCP is gated
C9016-2x
C9546 Series
C9547-01, -02
C9547-03, -04
Gate off Time
Gate Time
A
Gate Rise Time (Typ.)
Gate Fall Time (Typ.)
Delay Time
when MCP is gated
Jitter (Max.)
Output Level
Pulse Width
Output Impedance
Continuous Mode
Normally OFF, Turns ON when the gate signal is input
C-MOS Positive logic
50
0.5 ns
20 ns to DC
2 kHz
—
—
20 ns to DC
15 ns
15 ns
46 ns
±
2 ns
—
—
—
—
TTL Positive logic
8 ns to DC
30 kHz
10 kHz
20
μ
s Min.
5 ns to DC
3 ns
4 ns
36 ns
±
2 ns
86 ns
±
2 ns
2 V Positive logic (at 50
termination)
Gate time (FWHM)
50
5 ns to DC
3 ns to DC
2 ns
3 ns
15 ns to DC
10 ns to DC
8 ns
10 ns
Operation Mode
Gate Signal
Input
Gate Output
Gate Time
Monitor
NOTE:
A
Please refer to Figure 1 and Figure 3.
B
Built-in protection circuit
100
50
50
100
G
GATE INPUT PULSE WIDTH (ns)
DELAY TIME: 46 ns
±
2 ns
GATE INPUT PULSE WIDTH > 20 ns
A
B
GATE TIME * (FWHM)
NOTE:
A: 4.4 V to 5 V (50
)
B: 3.5 V (50
)
* Gate time (FWHM) is the same as gate input pulse width.
NORMALLY OFF
GATE
INPUT PULSE
GATE
OPERATION (I.I.)
JITTER 0.5 ns (MAX.)
DELAY TIME: Td
7 ns
±
1 ns
GATE INPUT PULSE WIDTH: C
A
B
GATE TIME (FWHM)
NOTE: A: 2 V to 5 V (50
)
B: 2 V (50
)
C: See Figure 3
D: 2 V (50
)
Td: 36 ns
±
2 ns (when MCP is ungated) 86 ns
±
2 ns (when MCP is gated)
MCP gate operation starts 26 ns prior to the rise edge of
GATE OPERATION and ends 26 ns after the fall edge.
GATE TIME (FWHM)
D
NORMALLY OFF
GATE
INPUT PULSE
GATE
OPERATION (I.I.)
GATE TIME
MONITOR
JITTER 0.5 ns (MAX.)
G
1
100
10
1
10
100
1000
GATE INPUT PULSE WIDTH (ns)
1000
WHEN MCP IS UNGATED
WHEN
MCP IS GATED
(10 kHz Max.)
INPUT PULSE LEVEL: 2 V (at 50
)