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參數(shù)資料
| 型號(hào)： | C9531 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SMD LED Lamps |
| 中文描述： | PCIX I / O系統(tǒng)時(shí)鐘發(fā)生器與EMI控制功能 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 176K |
| 代理商： | C9531 |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 6 of 14
APPROVED PRODUCT
C9531
Test Table
These output frequencies will be present when SMBus byte 0 bit 7 has been set to a logic 0 state.
Test Function
Clock
CLK(0:4)
Frequency
XIN/4
Outputs
REF
XIN
Table 3
Note:
1. XIN is the frequency of the clock that is present on the XIN input during test mode.
Byte 1: CPU Register (
1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
1
-
-
-
-
-
Description
Reserved
Reserved
REF Enable/Stopped
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 2: PCI Register
(1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
-
18
19
22
23
24
Description
Reserved
Reserved
Reserved
CLK4 Enable/Disable
CLK3 Enable/Disable
CLK2 Enable/Disable
CLK1 Enable/Disable
CLK0 Enable/Disable
Note: Stopping a clock indicated that the clock output is fixed in a logic low state. This effect will occur within 2 clock
cycles from the time the bit is set and does so in a manner so as not to cause any short or runt clock cycles. When the
stop is bit is changed from a stopped state to a running state the same (maximum 2 click latency) delay occurs with the
first cycle being full in period (for the frequency that is selected).
Internal Crystal Oscillator
This device will operate in two input reference clock configurations. In its simplest mode a 33.33 MHz fundamental cut
parallel resonant crystal is attached to the XIN and XOUT pins.
In the second mode a 33.33MHz input reference clock is driven in on the XIN clock from an external source. In this
application the XOUT pin is left disconnected.
Output Clock Tri-state Control
All of the clocks in the Bank may be placed in a tri-state condition by bringing their relevant OE pins to a logic low state.
This transition to and from a tristate and active condition is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
Both output enable pins contain internal pull-up resistors that will insure that a logic 1 (high) is maintained and sensed
by the device if no external circuitry is connected to these pins.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of
these control signals is determined by the SMBus register Byte 0 Bit 0. At initial power up this bit is set of a logic 1 state
and
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