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參數(shù)資料
| 型號： | C8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER ALTERA CORE |
| 中文描述： | 可編程DMA控制器ALTERA公司的核心 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大?。?/td> | 404K |
| 代理商： | C8237 |
Temporary Word Count Register (16 Bit Decrementor)
It will decrement the word count after each transfer. When the
value in the register goes from zero to FFFFH, a Terminal
Count (TC) will be generated.
Temporary Address Register (16 Bit Incremen-
tor/Decrementor)
Base on the mode of the address, the address will be decre-
mented or incremented after each transfer. And the
intermediate values of the address are stored in the Current
Address register during the transfer.
CAST, Inc. 11 Stonewall Court
Woodcliff Lake, NJ 076747 USA
tel 201-391-8300 fax 201-391-8694
Copyright CAST, Inc. 2004, All Rights Reserved.
Contents subject to change without notice. July 2003
Implementation Results
The following are typical performance and utilization results us-
ing a variety of Altera devices.
Supported
Family
Device
Tested
Utilization
Memory
Performance
F
max
LEs
Memory
bits
0
0
0
Cyclone
Stratix
Stratix-II
EP1C20-6
EP1S20-5
EP2S60-3
1,007
1,007
816
0
0
0
97 MHz
94 MHz
140 MHz
Support
The core as delivered is warranted against defects for three
years from purchase. Thirty days of phone and email technical
support are included, starting with the first interaction. Addi-
tional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and
rigorous code coverage measurements.
Deliverables
The core includes everything required for successful implemen-
tation:
Encrypted Licenses
Post-synthesis EDIF netlist
Assignment & Configuration
Symbol file
Include file
Wrapper for matching the I/O of the original device
Vectors for testbench
HDL Source Licenses
VHDL or Verilog RTL source code
Testbench
Wrapper for matching the I/O of the original device
Vectors for testbench
Expected results for testbench
Simulation and synthesis script
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