
Rev. 1.2
129
C8051F58x/F59x
14.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
UART1
0x0093
18
RI1 (SCON1.0)
TI1 (SCON1.1)
Y
N
ES1
(EIE2.3)
PS1
(EIP2.3)
Programmable Coun-
ter Array 1
0x009B
19
CF (PCA1CN.n)
CCFn (PCA1CN.n)
Y
N
EPCA1
(EIE2.4)
PPCA1
(EIP2.4)
Comparator2
0x00A3
20
CP2FIF (CPT2CN.4)
CP2RIF (CPT2CN.5)
N
ECP2
(EIE2.5)
PCP2
(EIP2.5)
Timer 4 Overflow
0x00AB
21
TF4H (TMR4CN.7)
TR4L (TMR4CN.6)
N
ET4
(EIE2.6)
PT4
(EIP2.6)
Timer 5 Overflow
0x00B3
22
TF5H (TMR5CN.7)
TF5L (TMR5CN.6)
N
ET5
(EIE2.7)
PT5
(EIP2.7)
*Note:
The LIN0INT bit is cleared by setting RSTINT (LINCTRL.3)
Table 14.1. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Bit
ad
dres
sab
le
?
Cle
a
re
d
by
HW?
Enable
Flag
Priority
Control