DOCUMENT CHANGE LIST
Revision 0.7 to Revision 0.8
Updated specification tables with most recently available characterization data.
Corrected references to configuring pins for Analog Mode - Port Latch must contain a '1'.
Added
Figure 8.2 showing power connection diagram without using on-chip regulator.
Section 9 : Removed references to "High Speed Analog Mode".
Table 11.2 : Corrected SFR Name P2MDIN on location 0xF3.
Section 14 : Corrected operational description of CRC engine.
Section 18, Important Note on page 151 : Added "and have the same behavior as P0 in Normal Mode." to
last sentence.
Section 19.2.2 : Inserted Step 3 "Release the crystal pins by writing ‘1's to the port latch."
cies.
Section 21: Corrected SMBus maximum rate to 1/20th system clock.
Table 21.4 : Made corrections to SMBus state descriptions.
Revision 0.8 to Revision 1.0
Updated specification tables with full characterization data.
Updated Flash write and erase procedures to include a write to FLSCL.3-0.
mended pull-up resistor.
Removed the "Optional GND Connection" from Figure 4.5. ’Typical QFN-28 Landing Diagram’ on page 48.
Revision 1.0 to Revision 1.1
Added information about 16-bit and 32-bit CRC algorithms in
C8051F410/1/2/3
268
Rev. 1.1