- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄17091 > C8051F360-TB (Silicon Laboratories Inc)BOARD TARGET/PROTO W/C8051F360 PDF資料下載
參數(shù)資料
| 型號(hào)： | C8051F360-TB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 41/288頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD TARGET/PROTO W/C8051F360 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | C8051F360 |
| 所含物品： | 板 |
| 產(chǎn)品目錄頁(yè)面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1407-ND - IC 8051 MCU 32K FLASH 48TQFP |
| 其它名稱： | 336-1412 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)
Rev. 1.0
135
C8051F360/1/2/3/4/5/6/7/8/9
13. Flash Memory
All devices include either 32 kB (C8051F360/1/2/3/4/5/6/7) or 16 kB (C8051F368/9) of on-chip, reprogram-
mable Flash memory for program code or non-volatile data storage. The Flash memory can be pro-
grammed in-system through the C2 interface, or by software using the MOVX write instructions. Once
cleared to logic ‘0’, a Flash bit must be erased to set it back to logic ‘1’. Bytes should be erased (set to
0xFF) before being reprogrammed. Flash write and erase operations are automatically timed by hardware
for proper execution. During a Flash erase or write, the FLBUSY bit in the FLSTAT register is set to ‘1’
(see SFR Definition 14.5). During this time, instructions that are located in the prefetch buffer or the branch
target cache can be executed, but the processor will stall until the erase or write is completed if instruction
data must be fetched from Flash memory. Interrupts that have been pre-loaded into the branch target
cache can also be serviced at this time, if the current code is also executing from the prefetch engine or
cache memory. Any interrupts that are not pre-loaded into cache, or that occur while the core is halted, will
be held in a pending state during the Flash write/erase operation, and serviced in priority order once the
Flash operation has completed. Refer to Table 13.2 for the electrical characteristics of the Flash memory.
13.1. Programming the Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “24. C2 Interface” on
The Flash memory can be programmed from software using the MOVX write instruction with the address
and data byte to be programmed provided as normal operands. Before writing to Flash memory using
MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic ‘1’. This directs the MOVX writes to Flash memory instead of to XRAM, which is the
default target. The PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is rec-
ommended that interrupts be disabled while the PSWE bit is logic ‘1’.
Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless
of the state of PSWE.
Note: To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled in any
system that includes code that writes and/or erases Flash memory from software. Furthermore,
there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Any attempt to write or erase Flash memory while the VDD Monitor disabled will
cause a Flash Error device reset.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed must be erased before a new value can be written.
Write/Erase timing is automatically controlled by hardware. Note that on the 32 k Flash devices, 1024
bytes beginning at location 0x7C00 are reserved. Flash writes and erases targeting the reserved area
should be avoided.
13.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| C8051F560-TB | BOARD PROTOTYPE W/C8051F560 |
| C8051F540-TB | BOARD PROTOTYPE W/C8051F540 |
| SDR-T1 | SCOTCH CODE REFILL T1 |
| C8051F530A-TB | BOARD TARGET/PROTO W/C8051F530A |
| RBM08DTKT | CONN EDGECARD 16POS DIP .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C8051F361 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Mixed Signal ISP Flash MCU Family |
| C8051F361-C-GQ | 功能描述:8051 C8051F36x Microcontroller IC 8-Bit 100MHz 32KB (32K x 8) FLASH 32-LQFP (7x7) 制造商:silicon labs 系列:C8051F36x 包裝:托盤(pán) 零件狀態(tài):Not For New Designs 核心處理器:8051 核心尺寸:8-位 速度:100MHz 連接性:SMBus（2 線/I2C），SPI，UART/USART 外設(shè):POR，PWM，溫度傳感器，WDT I/O 數(shù):29 程序存儲(chǔ)容量:32KB（32K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 容量:- RAM 容量:1K x 8 電壓 - 電源（Vcc/Vdd）:3 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 21x10b；D/A 1x10b 振蕩器類(lèi)型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:32-LQFP 供應(yīng)商器件封裝:32-LQFP（7x7） 標(biāo)準(zhǔn)包裝:250 |
| C8051F361-C-GQR | 功能描述:8051 C8051F36x Microcontroller IC 8-Bit 100MHz 32KB (32K x 8) FLASH 32-LQFP (7x7) 制造商:silicon labs 系列:C8051F36x 包裝:帶卷（TR） 零件狀態(tài):Not For New Designs 核心處理器:8051 核心尺寸:8-位 速度:100MHz 連接性:SMBus（2 線/I2C），SPI，UART/USART 外設(shè):POR，PWM，溫度傳感器，WDT I/O 數(shù):29 程序存儲(chǔ)容量:32KB（32K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 容量:- RAM 容量:1K x 8 電壓 - 電源（Vcc/Vdd）:3 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 21x10b；D/A 1x10b 振蕩器類(lèi)型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:32-LQFP 供應(yīng)商器件封裝:32-LQFP（7x7） 標(biāo)準(zhǔn)包裝:500 |
| C8051F361-GQ | 功能描述:8位微控制器 -MCU 32KB 100MIPS 10ADC 10DAC 32Pin MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051F361-GQ1 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Mixed Signal ISP Flash MCU Family |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。