bit in register RSTSRC. See Figure 9.2 for VDD monitor " />
參數(shù)資料
型號： C8051F302-GS
廠商： Silicon Laboratories Inc
文件頁數(shù)： 163/178頁
文件大?。?/td> 0K
描述： IC 8051 MCU 8K FLASH 14-SOIC
產(chǎn)品培訓模塊： Serial Communication Overview
標準包裝： 56
系列： C8051F30x
核心處理器： 8051
芯體尺寸： 8-位
速度： 25MHz
連通性： SMBus（2 線/I²C），UART/USART
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 8
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 622 (CN2011-ZH PDF)
配用： 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
其它名稱： 336-1537-5
Rev. 2.9
85
C8051F300/1/2/3/4/5
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic ‘1’ to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3.
External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4.
Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 s, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
9.5.
Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying
Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by
this reset.
9.6.
PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “16.3. Watchdog Timer Mode” on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
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C8051F303 功能描述:8位微控制器 -MCU 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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