bit in register RSTSRC. See Figure 9.2 for VDD monitor " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F301-GM
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 163/178闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC 8051 MCU 8K FLASH 11QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Serial Communication Overview
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 122
绯诲垪锛� C8051F30x
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 25MHz
閫i€氭€э細 SMBus锛�2 绶�/I²C锛�锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 8
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 8KB锛�8K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 256 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 10-VFDFN 瑁搁湶鐒婄洡
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 623 (CN2011-ZH PDF)
閰嶇敤锛� 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1319-ND - REFERENCE DESIGN STEPPER MOTOR
鍏跺畠鍚嶇ū锛� 336-1247
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Rev. 2.9
85
C8051F300/1/2/3/4/5
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic 鈥�1鈥� to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3.
External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4.
Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 s, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 鈥�1鈥�, signifying the MCD as the reset source; otherwise,
this bit reads 鈥�0鈥�. Writing a 鈥�1鈥� to the MCDRSF bit enables the Missing Clock Detector; writing a 鈥�0鈥� disables
it. The state of the RST pin is unaffected by this reset.
9.5.
Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 鈥�1鈥� to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0鈥�), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 鈥�1鈥� signifying
Comparator0 as the reset source; otherwise, this bit reads 鈥�0鈥�. The state of the RST pin is unaffected by
this reset.
9.6.
PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section 鈥�16.3. Watchdog Timer Mode鈥� on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 鈥�1鈥�. The state of the RST pin is unaffected by this reset.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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