參數(shù)資料
型號: C8051F300-GS
廠商: Silicon Laboratories Inc
文件頁數(shù): 126/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 14-SOIC
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 56
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 622 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名稱: 336-1535-5
Rev. 2.9
51
C8051F300/1/2/3/4/5
7.
Comparator0
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “l(fā)atched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see Section “12.2. Port I/O Initialization” on page 106). Comparator0 may also be used as a reset
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-
CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “12.3. General Purpose Port I/O” on page 108).
VDD
CPT0C
N
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
SET
CLR
D
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP
T
0
M
X CMX0N1
CMX0N0
CMX0P1
CMX0P0
CP
T
0
M
D
CP0MD1
CP0MD0
CP0
Rising-edge
Interrupt Flag
CP0
Falling-edge
Interrupt Flag
CP0
CP0A
Figure 7.1. Comparator0 Functional Block Diagram
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