參數(shù)資料
型號: C8051F300-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 54/178頁
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 11QFN
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 122
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 623 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名稱: 336-1245
Rev. 2.9
147
C8051F300/1/2/3/4/5
SFR Definition 15.1.
Bit7:
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
Bit6:
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
Bit5:
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
Bit4:
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
Bit3:
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 8.11).
Bit2:
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
Bit1:
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 8.11).
Bit0:
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
R/W
Reset Value
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0x88
TCON: Timer Control
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