參數(shù)資料
型號(hào): C8051F236R
廠商: Silicon Laboratories Inc
文件頁數(shù): 25/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1013-1
C8051F2xx
120
Rev. 1.6
If T1M (CKCON.4) is logic 1, then the above equation becomes:
T1_OVERFLOWRATE = (SYSCLK) / (256 – TH1).
If T1M (CKCON.4) is logic 0, then the above equation becomes:
T1_OVERFLOWRATE = (SYSCLK/12) / (256 – TH1).
The Timer 2 overflow rate, when in Baud Rate Generator Mode and using an internal clock source, is
determined solely by the Timer 2 16-bit reload value (RCAP2H:RCAP2L). The Timer 2 clock source is
fixed at SYSCLK/2. The Timer 2 overflow rate can be calculated as follows:
T2_OVERFLOWRATE = (SYSCLK/2) / (65536 – [RCAP2H:RCAP2L]).
Timer 2 can be selected as the baud rate generator for RX and/or TX by setting RCLK (T2CON.5) and/or
TCLK (T2CON.4), respectively. When either RCLK or TCLK is set to logic 1, Timer 2 interrupts are auto-
matically disabled and the timer is forced into Baud Rate Generator Mode with SYSCLK/2 as its clock
source. If a different timebase is required, setting the C/T2 bit (T2CON.1) to logic 1 will allow Timer 2 to be
clocked from the external input pin T2. See the Timers section for complete timer configuration details.
Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram
OR
RS-232
C8051Fxxx
RS-232
LEVEL
XLTR
TX
RX
C8051Fxxx
RX
TX
MCU
RX
TX
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