VDD = 3.0 V, 鈥�40" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F231
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 100/146闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC 8051 MCU 8K FLASH 32LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
绯诲垪锛� C8051F2xx
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 22
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 8KB锛�8K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 256 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
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鍖呰锛� 鎵樼洡
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C8051F2xx
Rev. 1.6
57
Table 8.1. Comparator Electrical Characteristics
VDD = 3.0 V, 鈥�40 to +85 脳C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Response Time1*
(CP+) 鈥� (CP鈥�) = 100 mV
鈥�
4
鈥�
s
Response Time2*
(CP+) 鈥� (CP鈥�) = 10 mV
鈥�
12
鈥�
s
Common Mode Rejection
Ratio
鈥�
1.5
4
mV/V
Positive Hysteresis1
CPnHYP1-0 = 00
鈥�
0
1
mV
Positive Hysteresis2
CPnHYP1-0 = 01
2
4.5
7
mV
Positive Hysteresis3
CPnHYP1-0 = 10
4
9
15
mV
Positive Hysteresis4
CPnHYP1-0 = 11
10
17
25
mV
Negative Hysteresis1
CPnHYN1-0 = 00
鈥�
0
1
mV
Negative Hysteresis2
CPnHYN1-0 = 01
2
4.5
7
mV
Negative Hysteresis3
CPnHYN1-0 = 10
4
9
15
mV
Negative Hysteresis4
CPnHYN1-0 = 11
10
17
25
mV
Inverting or Non-inverting
Input Voltage Range
鈥�0.25
鈥�
(VDD)
+ 0.25
V
Input Capacitance
鈥�
7
鈥�
pF
Input Bias Current
鈥�5
0.001
+5
nA
Input Offset Voltage
鈥�10
鈥�
+10
mV
POWER SUPPLY
Power-up Time
CPnEN from 0 to 1
鈥�
20
鈥�
s
Power Supply Rejection
鈥�
0.1
1
mV/V
Supply Current
Operating Mode
(each comparator) at DC
鈥�
1.5
4
A
*Note: CPnHYP1-0 = CPnHYN1-0 = 00.
鐩搁棞(gu膩n)PDF璩囨枡
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