C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
183
Table 13.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
RST Output Low Voltage
IOL = 8.5 mA, VDD = 2.7 to 3.6 V
——
0.6
V
RST Input High Voltage
0.7 x VDD
——
V
RST Input Low Voltage
—
0.3 x VDD
RST Input Leakage Current
RST = 0.0 V
—
50
—
A
VDD for RST Output Valid
1.0
—
V
AV+ for RST Output Valid
1.0
—
V
VDD POR Threshold (VRST)*
2.40
2.55
2.70
V
Minimum RST Low Time to Gen-
erate a System Reset
10
——ns
Reset Time Delay
RST rising edge after VDD
crosses VRST threshold
80
100
120
ms
Missing Clock Detector Timeout
Time from last system clock to
reset initiation
100
220
500
s
*Note: When operating at frequencies above 50 MHz, minimum
VDD supply Voltage is 3.0 V.