
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
185
14. Oscillators
The devices include a programmable internal oscillator and an external oscillator drive circuit. The internal
oscillator can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 14.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or the
on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in
Table 14.1Figure 14.1. Oscillator Diagram
14.1. Internal Calibrated Oscillator
All devices include a calibrated internal oscillator that defaults as the system clock after a system reset.
The internal oscillator period can be adjusted via the OSCICL register as defined by
SFR Definition 14.1.OSCICL is factory calibrated to obtain a 24.5 MHz frequency.
Table 14.1. Oscillator Electrical Characteristics
–40°C to +85°C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Calibrated Internal Oscillator
Frequency
24
24.5
25
MHz
Internal Oscillator Supply
Current (from VDD)
OSCICN.7 = 1
—
400
—
A
External Clock Frequency
0
—
30
MHz
TXCH (External Clock High Time)
15
—
ns
TXCL (External Clock Low Time)
15
—
ns
OSC
Calibrated
Internal
Oscillator
Input
Circuit
EN
SYSCLK
n
OSCICL
OSCICN
IO
SC
EN
IF
RD
Y
IF
C
N
1
IF
C
N
0
XTAL1
XTAL2
Option 2
VDD
XTAL1
Option 1
Option 4
XTAL1
OSCXCN
XT
LV
LD
XOSC
M
D
2
XOSC
M
D
1
XOSC
M
D
0
XF
CN
2
XF
CN
1
XF
CN
0
CLKSEL
CL
K
DI
V
1
CL
K
DI
V
0
CL
K
S
L
1
CL
K
S
L
0
00
01
PLL
10
Option 3
XTAL1
XTAL2
AGND
AV+