
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
25
Figure 1.5. C8051F130/132 Block Diagram
P0, P1,
P2, P3
Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
VDD
Monitor
Timers 0,
1, 2, 4
Timer 3/
RTC
P0
Drv
C
R
O
S
B
A
R
Port I/O
Config.
Crossbar
Config.
AV+
VDD
DGND
AGND
Reset
RST
Digital Power
Analog Power
Debug HW
Boundary Scan
P2.0
P2.7
P1.0/AIN2.0
P1.7/AIN2.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
VREF
ADC
100ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
VREF
TEMP
SENSOR
UART0
P3.0
P3.7
P3
Drv
MONEN
WDT
VREF0
Prog
Gain
CP0
CP1
C
T
L
P4 Latch
D
a
t
a
P7 Latch
A
d
r
P5 Latch
P6 Latch
P7.0/D0
P7.7/D7
P7
DRV
P5.0/A8
P5.7/A15
P5
DRV
P6.0/A0
P6.7/A7
P6
DRV
P4
DRV
P4.5/ALE
P4.6/RD
P4.7/WR
P4.0
P4.4
XTAL1
XTAL2
External Oscillator
Circuit
System
Clock
Calibrated Internal
Oscillator
PLL
Circuitry
FLASH
128kbyte
(‘F130)
64kbyte
(‘F132)
256 byte
RAM
SFR Bus
8
0
5
1
C
o
r
e
8kbyte
XRAM
External Data
Memory Bus
64x4 byte
cache