
C8051F060/1/2/3/4/5/6/7
296
Rev. 1.2
24.2.2. Capture Mode
In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the
Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX
input pin causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers
(RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6)
on page 151 for further information concerning the configuration of interrupt sources.
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config-
ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to
decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will
occur if enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn
(TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4
respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable a captures. If EXENn
is cleared, transitions on TnEX will be ignored.
TMRnL
TMRnH
TRn
TCLK
Interrupt
TM
Rn
CN
EXFn
EXENn
TRn
C/Tn
CP/RLn
TFn
SYSCLK
12
2
TMRnCF
D
C
E
N
T
n
O
E
T
O
G
n
T
n
M
1
T
n
M
0
Toggle Logic
Tn
(Port Pin)
0
1
0
EXENn
Crossbar
TnEX
RCAPnL
RCAPnH
0xFF
8
External Clock
(XTAL1)
Tn
Crossbar
OVF
Capture
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram