SMBus provides a clock synchronization mechanism, similar to I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� C8051F040
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 160/328闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC 8051 MCU 64K FLASH 100TQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� C8051F04x
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 25MHz
閫i€氭€э細 CAN锛孍BI/EMI锛孲MBus锛�2 绶�/I²C锛�锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 64
绋嬪簭瀛樺劜鍣ㄥ閲忥細 64KB锛�64K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 4.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8b锛�13x12b; D/A 2x10b锛�2x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
鍖呰锛� 鎵樼洡
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C8051F040/1/2/3/4/5/6/7
242
Rev. 1.5
19.2.2. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
19.2.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a 鈥渢imeout鈥� condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
19.2.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus
is designated as free. If an SMBus device is waiting to generate a Master START, the START will be gen-
erated following the bus free timeout.
19.3. SMBus Transfer Modes
The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the
interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave
Transmitter, or Slave Receiver. See Table 19.1 for transfer mode status decoding using the SMB0STA sta-
tus register. The following mode descriptions illustrate an interrupt-driven SMBus0 application; SMBus0
may alternatively be operated in polled mode.
19.3.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START
condition and then transmits the first byte containing the address of the target slave device and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ACK) from the
slave after each byte. To indicate the end of the serial transfer, SMBus0 generates a STOP condition.
Figure 19.4. Typical Master Transmitter Sequence
A
S
W
P
Data Byte
SLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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