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DS003-1.1 JAN02
  2002 Cygnal Integrated Products, Inc.
PRELIMINARY
C8051F020/1/2/3
Figure 15.1. FLASH Program Memory Map and Security Bytes.........................................139Figure 15.2. FLACL: FLASH Access Limit .........................................................................140
Figure 15.3. FLSCL: FLASH Memory Control....................................................................141
Figure 15.4. PSCTL: Program Store Read/Write Control.....................................................142
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................143
Figure 16.1. EMI0CN: External Memory Interface Control.................................................145
Figure 16.2. EMI0CF: External Memory Configuration.......................................................145
Figure 16.3. Multiplexed Configuration Example.................................................................146
Figure 16.4. Non-multiplexed Configuration Example.........................................................147
Figure 16.5. EMIF Operating Modes.....................................................................................148
Figure 16.6. EMI0TC: External Memory Timing Control....................................................150
Figure 16.7. Non-multiplexed 16-bit MOVX Timing...........................................................151
Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................152
Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................153
Figure 16.10. Multiplexed 16-bit MOVX Timing.................................................................154
Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................155
Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................156
Table 16.1. AC Parameters for External Memory Interface.................................................157
17. PORT INPUT/OUTPUT.....................................................................................................159
Figure 17.1. Port I/O Cell Block Diagram.............................................................................159
Table 17.1. Port I/O DC Electrical Characteristics ..............................................................159
Figure 17.2. Lower Port I/O Functional Block Diagram.......................................................160
Figure 17.3. Priority Crossbar Decode Table........................................................................161
Figure 17.4. Priority Crossbar Decode Table........................................................................164
Figure 17.5. Priority Crossbar Decode Table........................................................................165
Figure 17.6. Crossbar Example: ............................................................................................167
Figure 17.7. XBR0: Port I/O Crossbar Register 0.................................................................168
Figure 17.8. XBR1: Port I/O Crossbar Register 1.................................................................169
Figure 17.9. XBR2: Port I/O Crossbar Register 2.................................................................170
Figure 17.10. P0: Port0 Data Register...................................................................................171
Figure 17.11. P0MDOUT: Port0 Output Mode Register.......................................................171
Figure 17.12. P1: Port1 Data Register...................................................................................172
Figure 17.13. P1MDIN: Port1 Input Mode Register.............................................................172
Figure 17.14. P1MDOUT: Port1 Output Mode Register.......................................................173
Figure 17.15. P2: Port2 Data Register...................................................................................173
Figure 17.16. P2MDOUT: Port2 Output Mode Register.......................................................173
Figure 17.17. P3: Port3 Data Register...................................................................................174
Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................174
Figure 17.19. P3IF: Port3 Interrupt Flag Register.................................................................175
Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register...................................................177
Figure 17.21. P4: Port4 Data Register...................................................................................178
Figure 17.22. P5: Port5 Data Register...................................................................................178
Figure 17.23. P6: Port6 Data Register...................................................................................179
Figure 17.24. P7: Port7 Data Register...................................................................................179